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Merge pull request #5277 from YosysHQ/krys/fix_4983_alt
autoname: Avoid integer overflow
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KrystalDelusion
GitHub
commit
7ebd972165
2 changed files with 237 additions and 30 deletions
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@ -22,11 +22,24 @@
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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int autoname_worker(Module *module, const dict<Wire*, int>& wire_score)
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typedef struct name_proposal {
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string name;
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unsigned int score;
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name_proposal() : name(""), score(-1) { }
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name_proposal(string name, unsigned int score) : name(name), score(score) { }
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bool operator<(const name_proposal &other) const {
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if (score != other.score)
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return score < other.score;
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else
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return name.length() < other.name.length();
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}
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} name_proposal;
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int autoname_worker(Module *module, const dict<Wire*, unsigned int>& wire_score)
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{
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dict<Cell*, pair<int, string>> proposed_cell_names;
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dict<Wire*, pair<int, string>> proposed_wire_names;
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int best_score = -1;
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dict<Cell*, name_proposal> proposed_cell_names;
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dict<Wire*, name_proposal> proposed_wire_names;
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name_proposal best_name;
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for (auto cell : module->selected_cells()) {
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if (cell->name[0] == '$') {
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@ -36,14 +49,14 @@ int autoname_worker(Module *module, const dict<Wire*, int>& wire_score)
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if (bit.wire != nullptr && bit.wire->name[0] != '$') {
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if (suffix.empty())
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suffix = stringf("_%s_%s", log_id(cell->type), log_id(conn.first));
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string new_name(bit.wire->name.str() + suffix);
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int score = wire_score.at(bit.wire);
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if (cell->output(conn.first)) score = 0;
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score = 10000*score + new_name.size();
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if (!proposed_cell_names.count(cell) || score < proposed_cell_names.at(cell).first) {
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if (best_score < 0 || score < best_score)
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best_score = score;
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proposed_cell_names[cell] = make_pair(score, new_name);
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name_proposal proposed_name(
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bit.wire->name.str() + suffix,
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cell->output(conn.first) ? 0 : wire_score.at(bit.wire)
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);
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if (!proposed_cell_names.count(cell) || proposed_name < proposed_cell_names.at(cell)) {
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if (proposed_name < best_name)
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best_name = proposed_name;
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proposed_cell_names[cell] = proposed_name;
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}
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}
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}
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@ -54,37 +67,44 @@ int autoname_worker(Module *module, const dict<Wire*, int>& wire_score)
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if (bit.wire != nullptr && bit.wire->name[0] == '$' && !bit.wire->port_id) {
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if (suffix.empty())
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suffix = stringf("_%s", log_id(conn.first));
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string new_name(cell->name.str() + suffix);
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int score = wire_score.at(bit.wire);
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if (cell->output(conn.first)) score = 0;
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score = 10000*score + new_name.size();
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if (!proposed_wire_names.count(bit.wire) || score < proposed_wire_names.at(bit.wire).first) {
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if (best_score < 0 || score < best_score)
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best_score = score;
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proposed_wire_names[bit.wire] = make_pair(score, new_name);
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name_proposal proposed_name(
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cell->name.str() + suffix,
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cell->output(conn.first) ? 0 : wire_score.at(bit.wire)
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);
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if (!proposed_wire_names.count(bit.wire) || proposed_name < proposed_wire_names.at(bit.wire)) {
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if (proposed_name < best_name)
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best_name = proposed_name;
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proposed_wire_names[bit.wire] = proposed_name;
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}
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}
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}
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}
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}
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int count = 0;
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// compare against double best score for following comparisons so we don't
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// pre-empt a future iteration
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best_name.score *= 2;
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for (auto &it : proposed_cell_names) {
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if (best_score*2 < it.second.first)
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if (best_name < it.second)
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continue;
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IdString n = module->uniquify(IdString(it.second.second));
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IdString n = module->uniquify(IdString(it.second.name));
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log_debug("Rename cell %s in %s to %s.\n", log_id(it.first), log_id(module), log_id(n));
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module->rename(it.first, n);
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count++;
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}
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for (auto &it : proposed_wire_names) {
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if (best_score*2 < it.second.first)
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if (best_name < it.second)
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continue;
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IdString n = module->uniquify(IdString(it.second.second));
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IdString n = module->uniquify(IdString(it.second.name));
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log_debug("Rename wire %s in %s to %s.\n", log_id(it.first), log_id(module), log_id(n));
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module->rename(it.first, n);
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count++;
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}
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return proposed_cell_names.size() + proposed_wire_names.size();
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return count;
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}
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struct AutonamePass : public Pass {
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@ -110,12 +130,13 @@ struct AutonamePass : public Pass {
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// }
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break;
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}
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extra_args(args, argidx, design);
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log_header(design, "Executing AUTONAME pass.\n");
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for (auto module : design->selected_modules())
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{
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dict<Wire*, int> wire_score;
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dict<Wire*, unsigned int> wire_score;
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for (auto cell : module->selected_cells())
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for (auto &conn : cell->connections())
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for (auto bit : conn.second)
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@ -1,10 +1,11 @@
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# prefer output name
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design -reset
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read_rtlil <<EOT
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autoidx 2
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module \top
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wire output 3 $y
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wire output 3 \y
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wire input 1 \a
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wire input 2 \b
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cell $and \b_$and_B
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cell $and $name
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parameter \A_SIGNED 0
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parameter \A_WIDTH 1
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parameter \B_SIGNED 0
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@ -12,8 +13,193 @@ module \top
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parameter \Y_WIDTH 1
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connect \A \a
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connect \B \b
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connect \Y \y
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end
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end
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EOT
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logger -expect log "Rename cell .name in top to y_.and_Y" 1
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logger -expect log "Renamed 1 objects" 1
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debug autoname
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logger -check-expected
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# fallback to shortest name if output is private
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design -reset
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read_rtlil <<EOT
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autoidx 2
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module \top
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wire output 3 $y
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wire input 1 \ab
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wire input 2 \abcd
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cell $or $name
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parameter \A_SIGNED 0
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parameter \A_WIDTH 1
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parameter \B_SIGNED 0
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parameter \B_WIDTH 1
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parameter \Y_WIDTH 1
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connect \A \ab
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connect \B \abcd
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connect \Y $y
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end
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end
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EOT
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autoname
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logger -expect log "Rename cell .name in top to ab_.or_A" 1
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logger -expect log "Renamed 1 objects" 1
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debug autoname
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logger -check-expected
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# prefer low fanout over low name length
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design -reset
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read_rtlil <<EOT
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module \top
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wire output 1 $y
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wire input 2 \a
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wire input 3 \bcd
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wire input 4 \c_has_a_long_name
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cell $and $name
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parameter \A_SIGNED 0
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parameter \A_WIDTH 1
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parameter \B_SIGNED 0
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parameter \B_WIDTH 1
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parameter \Y_WIDTH 1
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connect \A \a
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connect \B \bcd
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connect \Y $y
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end
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cell $or $name2
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parameter \A_SIGNED 0
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parameter \A_WIDTH 1
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parameter \B_SIGNED 0
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parameter \B_WIDTH 1
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parameter \Y_WIDTH 1
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connect \A \a
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connect \B \c_has_a_long_name
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connect \Y $y
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end
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end
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EOT
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logger -expect log "Rename cell .name in top to bcd_.and_B" 1
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logger -expect log "Rename cell .name2 in top to c_has_a_long_name_.or_B" 1
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logger -expect log "Renamed 2 objects" 1
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debug autoname
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logger -check-expected
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# names are unique
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design -reset
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read_rtlil <<EOT
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module \top
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wire output 3 \y
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wire input 1 \a
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wire input 2 \b
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cell $and $name
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parameter \A_SIGNED 0
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parameter \A_WIDTH 1
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parameter \B_SIGNED 0
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parameter \B_WIDTH 1
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parameter \Y_WIDTH 1
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connect \A \a
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connect \B \b
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connect \Y \y
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end
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cell $and $name2
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parameter \A_SIGNED 0
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parameter \A_WIDTH 1
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parameter \B_SIGNED 0
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parameter \B_WIDTH 1
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parameter \Y_WIDTH 1
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connect \A \a
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connect \B \b
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connect \Y \y
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end
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end
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EOT
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logger -expect log "Rename cell .name in top to y_.and_Y" 1
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logger -expect log "Rename cell .name2 in top to y_.and_Y_1" 1
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logger -expect log "Renamed 2 objects" 1
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debug autoname
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logger -check-expected
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# wires get autonames too
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design -reset
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read_rtlil <<EOT
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module \top
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wire output 1 $y
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wire input 2 \a
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wire input 3 \bcd
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wire $c
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wire $d
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wire $e
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cell $__unknown $name
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parameter \A_SIGNED 0
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parameter \A_WIDTH 1
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parameter \B_SIGNED 0
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parameter \B_WIDTH 1
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parameter \Y_WIDTH 1
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connect \A \a
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connect \B \bcd
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connect \Y $c
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end
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cell $or \or
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parameter \A_SIGNED 0
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parameter \A_WIDTH 1
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parameter \B_SIGNED 0
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parameter \B_WIDTH 1
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parameter \Y_WIDTH 1
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connect \A \a
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connect \B \bcd
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connect \Y $d
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end
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cell $or $name2
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parameter \A_SIGNED 0
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parameter \A_WIDTH 1
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parameter \B_SIGNED 0
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parameter \B_WIDTH 1
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parameter \Y_WIDTH 1
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connect \A $c
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connect \B $d
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connect \Y $e
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end
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cell $and $name3
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parameter \A_SIGNED 0
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parameter \A_WIDTH 1
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parameter \B_SIGNED 0
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parameter \B_WIDTH 1
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parameter \Y_WIDTH 1
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connect \A $c
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connect \B $e
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connect \Y $y
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end
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end
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EOT
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design -save order_test
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# wires are named for being cell outputs
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logger -expect log "Rename wire .d in top to or_Y" 1
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logger -expect log "Rename cell .name2 in top to or_Y_.or_B" 1
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logger -expect log "Renamed 2 objects" 1
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debug autoname t:$or
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logger -check-expected
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# $name gets shortest name (otherwise bcd_$__unknown_B)
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logger -expect log "Rename cell .name in top to a_.__unknown_A" 1
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# another output wire
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logger -expect log "Rename wire .e in top to or_Y_.or_B_Y" 1
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logger -expect log "Renamed 4 objects" 1
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debug autoname
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logger -check-expected
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# don't rename prematurely (some objects should be named after $name2)
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design -load order_test
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# $c gets shortest name, since the cell driving it doesn't have known port
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# directions (otherwise a_$__unknown_A_Y)
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logger -expect log "Rename wire .c in top to or_Y_.or_B_A" 1
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# $name3 named for lowest fanout wire (otherwise a_$__unknown_A_Y_$and_A)
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logger -expect log "Rename cell .name3 in top to or_Y_.or_B_Y_.and_B" 1
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logger -expect log "Renamed 6 objects" 1
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debug autoname
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logger -check-expected
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