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Code Activity
9820 commits 103 branches 53 tags 50 MiB
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3283 commits

Author SHA1 Message Date
Eddie Hung
792cd31052 Add comments for xilinx_dsp_cascade 2019-10-04 22:31:04 -07:00
Eddie Hung
12fd2ec4f0 Improve comments for xilinx_dsp_CREG 2019-10-04 22:31:04 -07:00
Eddie Hung
14e4aeece6 Fix comment 2019-10-04 22:31:04 -07:00
Eddie Hung
8027ebf05b Restore optimisation for sigM.empty() 2019-10-04 22:31:04 -07:00
Eddie Hung
77d7a5c14a Retry on fixing TODOs 2019-10-04 22:31:04 -07:00
Eddie Hung
52583ecff8 Revert "Fix TODOs" 
This reverts commit 8674a6c68d563908014d16671567459499c6dc99.
 2019-10-04 22:31:04 -07:00
Eddie Hung
6d68972619 More comments, cleanup 2019-10-04 22:31:04 -07:00
Eddie Hung
7de9c33931 Fix TODOs 2019-10-04 22:31:04 -07:00
Eddie Hung
983068103e Consistency 2019-10-04 22:31:04 -07:00
Eddie Hung
cf82b38478 Add comments for xilinx_dsp 2019-10-04 22:31:04 -07:00
Eddie Hung
a5ac33f230 Merge branch 'master' into eddie/abc_to_abc9 2019-10-04 17:53:20 -07:00
Eddie Hung
f0cadb0de8 Fix from merge 2019-10-04 17:52:19 -07:00
Eddie Hung
bbc0e06af3 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-10-04 17:39:08 -07:00
Eddie Hung
0acc51c3d8 Add temporary abc9 -nomfs and use for synth_xilinx -abc9 2019-10-04 17:35:43 -07:00
Eddie Hung
7959e9d6b2 Fix merge issues 2019-10-04 17:21:14 -07:00
Eddie Hung
7a45cd5856 Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff 2019-10-04 16:58:55 -07:00
Eddie Hung
74ef8feeaf Fix xilinx_dsp for unsigned extensions 2019-10-04 16:46:15 -07:00
Eddie Hung
aae2b9fd9c Rename abc_* names/attributes to more precisely be abc9_* 2019-10-04 11:04:10 -07:00
Eddie Hung
84f978bdc2 Add -async2sync to help text as per @daveshah1 2019-10-04 10:17:46 -07:00
Miodrag Milanovic
c0b14cfea7 Fixes for MSVC build 2019-10-04 16:29:46 +02:00
Eddie Hung
549d6ea467 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-10-03 10:55:23 -07:00
Eddie Hung
a9efd2e81c Restore part of doc 2019-10-03 10:51:53 -07:00
Eddie Hung
7a6dec1cef Add new -async2sync option 2019-10-03 10:30:51 -07:00
Eddie Hung
8765ec3c27 Revert "equiv_opt to call async2sync when not -multiclock like SymbiYosys" 
This reverts commit a39505e329.
 2019-10-03 10:07:15 -07:00
Eddie Hung
c6d15c9aad Revert "Update doc for equiv_opt" 
This reverts commit a274b7cc86.
 2019-10-03 10:07:03 -07:00
Clifford Wolf
0e05424885
Merge pull request #1422 from YosysHQ/eddie/aigmap_select 
Add -select option to aigmap
 2019-10-03 11:54:04 +02:00
Clifford Wolf
afdc990595
Merge pull request #1429 from YosysHQ/clifford/checkmapped 
Add "check -mapped"
 2019-10-03 11:50:53 +02:00
Clifford Wolf
3e27b2846b Add "check -allow-tbuf" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-10-03 11:49:56 +02:00
Eddie Hung
e9645c7fa7 Fix broken CI, check reset even for constants, trim rstmux 2019-10-02 21:26:26 -07:00
Eddie Hung
c6a55d948a Merge branch 'eddie/fix_sat_init' into eddie/fix1427 2019-10-02 18:07:38 -07:00
Eddie Hung
d99810ad8a Refactor peepopt_dffmux and be sensitive to \init when trimming 2019-10-02 18:01:45 -07:00
Eddie Hung
f46ac1df9f Be mindful that sigmap(wire) could have dupes when checking \init 2019-10-02 16:08:46 -07:00
Eddie Hung
265a655ef9 Also rename cells with _TECHMAP_REPLACE_. prefix, as per @cliffordwolf 2019-10-02 12:43:35 -07:00
Clifford Wolf
45e4c040d7 Add "check -mapped" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-10-02 13:35:03 +02:00
Eddie Hung
edc3780723 techmap wires named _TECHMAP_REPLACE_.<identifier> to create alias 2019-09-30 17:20:12 -07:00
Eddie Hung
1b96d29174 No need to punch ports at all 2019-09-30 17:02:20 -07:00
Eddie Hung
390b960c8c Resolve FIXME on calling proc just once 2019-09-30 16:37:29 -07:00
Eddie Hung
e529872b01 Remove need for $currQ port connection 2019-09-30 16:33:40 -07:00
Eddie Hung
f2f19df2d4 Add -select option to aigmap 2019-09-30 15:26:29 -07:00
Eddie Hung
e0aa772663 Add comment 2019-09-30 15:19:02 -07:00
Eddie Hung
a6994c5f16 scc call on active module module only, plus cleanup 2019-09-30 12:57:19 -07:00
Eddie Hung
8684b58bed Merge remote-tracking branch 'origin/master' into xaig_dff 2019-09-30 12:29:35 -07:00
Eddie Hung
a274b7cc86 Update doc for equiv_opt 2019-09-30 10:59:56 -07:00
Miodrag Milanović
0d27ffd4e6
Merge pull request #1416 from YosysHQ/mmicko/frontend_binary_in 
Open aig frontend as binary file
 2019-09-30 17:49:23 +02:00
Clifford Wolf
0d28e45dcb
Merge pull request #1412 from YosysHQ/eddie/equiv_opt_async2sync 
equiv_opt to call async2sync when not -multiclock like SymbiYosys
 2019-09-30 17:04:21 +02:00
Clifford Wolf
10e57f3880 Fix $dlatch handling in async2sync 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-09-30 14:58:23 +02:00
Eddie Hung
1123c09588 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-09-29 19:39:12 -07:00
Eddie Hung
8474c5b366
Merge pull request #1359 from YosysHQ/xc7dsp 
DSP inference for Xilinx (improved for ice40, initial support for ecp5)
 2019-09-29 11:26:22 -07:00
Eddie Hung
5a4011e8c9 Fix "scc" call inside abc9 to consider all wires 2019-09-29 09:58:00 -07:00
Miodrag Milanovic
3f70c1fd26 Open aig frontend as binary file 2019-09-29 13:22:11 +02:00