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Consistency

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This commit is contained in:
Eddie Hung 2019-10-04 12:43:19 -07:00
parent cf82b38478
commit 983068103e
1 changed files with 3 additions and 3 deletions
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6
passes/pmgen/xilinx_dsp_CREG.pmg
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@ -45,7 +45,7 @@ match dsp
select nusers(port(dsp, \C, SigSpec())) > 1
endmatch
code sigC sigP
code sigC sigP clock
unextend = [](const SigSpec &sig) {
int i;
for (i = GetSize(sig)-1; i > 0; i--)
@ -71,6 +71,8 @@ code sigC sigP
}
else
sigP = P;
clock = port(dsp, \CLK, SigBit());
endcode
// (2) Match the driver of the 'C' input to a possible $dff cell (CREG)
@ -82,8 +84,6 @@ code argQ ffC ffCcemux ffCrstmux ffCcepol ffCrstpol sigC clock
if (sigC == sigP)
reject;
clock = port(dsp, \CLK, SigBit());
argQ = sigC;
subpattern(in_dffe);
if (dff) {