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Fix comment

This commit is contained in:
Eddie Hung 2019-10-04 21:45:31 -07:00
parent 8027ebf05b
commit 14e4aeece6

View file

@ -614,7 +614,7 @@ struct XilinxDspPass : public Pass {
xilinx_simd_pack(module, module->selected_cells());
// Match for all features ([ABDMP][12]?REG, pre-adder,
// (post-adder, pattern detector, etc.) except for CREG
// post-adder, pattern detector, etc.) except for CREG
{
xilinx_dsp_pm pm(module, module->selected_cells());
pm.run_xilinx_dsp_pack(xilinx_dsp_pack);