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Fix merge issues

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This commit is contained in:
Eddie Hung 2019-10-04 17:21:14 -07:00
parent 7a45cd5856
commit 7959e9d6b2
6 changed files with 14 additions and 21 deletions
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4
passes/techmap/abc9.cc
View file

@ -459,7 +459,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
dict<IdString, bool> abc9_box;
vector<RTLIL::Cell*> boxes;
for (auto cell : module->selected_cells()) {
if (cell->type.in(ID($_AND_), ID($_NOT_), ID($__ABC_FF_))) {
if (cell->type.in(ID($_AND_), ID($_NOT_), ID($__ABC9_FF_))) {
module->remove(cell);
continue;
}
@ -533,7 +533,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
cell_stats[mapped_cell->type]++;
RTLIL::Cell *existing_cell = nullptr;
if (mapped_cell->type.in(ID($lut), ID($__ABC_FF_))) {
if (mapped_cell->type.in(ID($lut), ID($__ABC9_FF_))) {
if (mapped_cell->type == ID($lut) &&
GetSize(mapped_cell->getPort(ID::A)) == 1 &&
mapped_cell->getParam(ID(LUT)) == RTLIL::Const::from_string("01")) {

8
passes/techmap/techmap.cc
View file

@ -256,14 +256,6 @@ struct TechmapWorker
if (w->attributes.count(ID(src)))
w->add_strpool_attribute(ID(src), extra_src_attrs);
}
if (it.second->name.begins_with("\\_TECHMAP_REPLACE_")) {
IdString replace_name = stringf("%s%s", orig_cell_name.c_str(), it.second->name.c_str() + strlen("\\_TECHMAP_REPLACE_"));
Wire *replace_w = module->addWire(replace_name, it.second);
module->connect(replace_w, w);
}
design->select(module, w);
if (it.second->name.begins_with("\\_TECHMAP_REPLACE_.")) {