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No need to punch ports at all

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This commit is contained in:
Eddie Hung 2019-09-30 17:02:20 -07:00
parent 390b960c8c
commit 1b96d29174
2 changed files with 24 additions and 13 deletions
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13
passes/techmap/abc9.cc
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@ -1121,19 +1121,6 @@ struct Abc9Pass : public Pass {
Pass::call_on_module(design, derived_module, "proc");
SigMap derived_sigmap(derived_module);
Wire *currQ = derived_module->wire("\\$currQ");
if (currQ == NULL)
log_error("'\\$currQ' is not a wire present in module '%s'.\n", log_id(cell->type));
log_assert(!currQ->port_output);
if (!currQ->port_input) {
currQ->port_input = true;
derived_module->ports.push_back(currQ->name);
currQ->port_id = GetSize(derived_module->ports);
#ifndef NDEBUG
derived_module->check();
#endif
}
SigSpec pattern;
SigSpec with;
for (auto &conn : cell->connections()) {