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yosys/passes
2019-10-02 18:07:38 -07:00
..
cmds Improve "portlist" command 2019-09-25 09:20:38 +02:00
equiv Update doc for equiv_opt 2019-09-30 10:59:56 -07:00
fsm RTLIL::S{0,1} -> State::S{0,1} 2019-08-07 11:12:38 -07:00
hierarchy Adopt @cliffordwolf's suggestion 2019-09-03 12:18:50 -07:00
memory stoi -> atoi 2019-08-07 11:09:17 -07:00
opt Fix handling of z_digit "?" and fix optimization of cmp with "z" 2019-09-13 13:39:39 +02:00
pmgen Refactor peepopt_dffmux and be sensitive to \init when trimming 2019-10-02 18:01:45 -07:00
proc proc_clean: fix order of switch insertion. 2019-08-19 16:44:23 +00:00
sat Be mindful that sigmap(wire) could have dupes when checking \init 2019-10-02 16:08:46 -07:00
techmap Merge pull request #1416 from YosysHQ/mmicko/frontend_binary_in 2019-09-30 17:49:23 +02:00
tests Document (* gentb_skip *) attr for test_autotb 2019-09-06 13:28:15 -07:00