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Merge remote-tracking branch 'origin/master' into xaig_dff

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This commit is contained in:
Eddie Hung 2019-10-03 10:55:23 -07:00
commit 549d6ea467
20 changed files with 374 additions and 86 deletions
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82
passes/cmds/check.cc
View file

@ -41,14 +41,24 @@ struct CheckPass : public Pass {
log("\n");
log(" - used wires that do not have a driver\n");
log("\n");
log("When called with -noinit then this command also checks for wires which have\n");
log("the 'init' attribute set.\n");
log("Options:\n");
log("\n");
log("When called with -initdrv then this command also checks for wires which have\n");
log("the 'init' attribute set and aren't driven by a FF cell type.\n");
log(" -noinit\n");
log(" Also check for wires which have the 'init' attribute set.\n");
log("\n");
log("When called with -assert then the command will produce an error if any\n");
log("problems are found in the current design.\n");
log(" -initdrv\n");
log(" Also check for wires that have the 'init' attribute set and are not\n");
log(" driven by an FF cell type.\n");
log("\n");
log(" -mapped\n");
log(" Also check for internal cells that have not been mapped to cells of the\n");
log(" target architecture.\n");
log("\n");
log(" -allow-tbuf\n");
log(" Modify the -mapped behavior to still allow $_TBUF_ cells.\n");
log("\n");
log(" -assert\n");
log(" Produce a runtime error if any problems are found in the current design.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@ -56,6 +66,8 @@ struct CheckPass : public Pass {
int counter = 0;
bool noinit = false;
bool initdrv = false;
bool mapped = false;
bool allow_tbuf = false;
bool assert_mode = false;
size_t argidx;
@ -68,6 +80,14 @@ struct CheckPass : public Pass {
initdrv = true;
continue;
}
if (args[argidx] == "-mapped") {
mapped = true;
continue;
}
if (args[argidx] == "-allow-tbuf") {
allow_tbuf = true;
continue;
}
if (args[argidx] == "-assert") {
assert_mode = true;
continue;
@ -135,29 +155,37 @@ struct CheckPass : public Pass {
TopoSort<string> topo;
for (auto cell : module->cells())
for (auto &conn : cell->connections()) {
SigSpec sig = sigmap(conn.second);
bool logic_cell = yosys_celltypes.cell_evaluable(cell->type);
if (cell->input(conn.first))
for (auto bit : sig)
if (bit.wire) {
{
if (mapped && cell->type.begins_with("$") && design->module(cell->type) == nullptr) {
if (allow_tbuf && cell->type == ID($_TBUF_)) goto cell_allowed;
log_warning("Cell %s.%s is an unmapped internal cell of type %s.\n", log_id(module), log_id(cell), log_id(cell->type));
counter++;
cell_allowed:;
}
for (auto &conn : cell->connections()) {
SigSpec sig = sigmap(conn.second);
bool logic_cell = yosys_celltypes.cell_evaluable(cell->type);
if (cell->input(conn.first))
for (auto bit : sig)
if (bit.wire) {
if (logic_cell)
topo.edge(stringf("wire %s", log_signal(bit)),
stringf("cell %s (%s)", log_id(cell), log_id(cell->type)));
used_wires.insert(bit);
}
if (cell->output(conn.first))
for (int i = 0; i < GetSize(sig); i++) {
if (logic_cell)
topo.edge(stringf("wire %s", log_signal(bit)),
stringf("cell %s (%s)", log_id(cell), log_id(cell->type)));
used_wires.insert(bit);
topo.edge(stringf("cell %s (%s)", log_id(cell), log_id(cell->type)),
stringf("wire %s", log_signal(sig[i])));
if (sig[i].wire)
wire_drivers[sig[i]].push_back(stringf("port %s[%d] of cell %s (%s)",
log_id(conn.first), i, log_id(cell), log_id(cell->type)));
}
if (cell->output(conn.first))
for (int i = 0; i < GetSize(sig); i++) {
if (logic_cell)
topo.edge(stringf("cell %s (%s)", log_id(cell), log_id(cell->type)),
stringf("wire %s", log_signal(sig[i])));
if (sig[i].wire)
wire_drivers[sig[i]].push_back(stringf("port %s[%d] of cell %s (%s)",
log_id(conn.first), i, log_id(cell), log_id(cell->type)));
}
if (!cell->input(conn.first) && cell->output(conn.first))
for (auto bit : sig)
if (bit.wire) wire_drivers_count[bit]++;
if (!cell->input(conn.first) && cell->output(conn.first))
for (auto bit : sig)
if (bit.wire) wire_drivers_count[bit]++;
}
}
pool<SigBit> init_bits;

14
passes/techmap/techmap.cc
View file

@ -265,6 +265,12 @@ struct TechmapWorker
}
design->select(module, w);
if (it.second->name.begins_with("\\_TECHMAP_REPLACE_.")) {
IdString replace_name = stringf("%s%s", orig_cell_name.c_str(), it.second->name.c_str() + strlen("\\_TECHMAP_REPLACE_"));
Wire *replace_w = module->addWire(replace_name, it.second);
module->connect(replace_w, w);
}
}
SigMap tpl_sigmap(tpl);
@ -386,6 +392,8 @@ struct TechmapWorker
if (techmap_replace_cell)
c_name = orig_cell_name;
else if (it.second->name.begins_with("\\_TECHMAP_REPLACE_."))
c_name = stringf("%s%s", orig_cell_name.c_str(), c_name.c_str() + strlen("\\_TECHMAP_REPLACE_"));
else
apply_prefix(cell->name, c_name);
@ -1206,6 +1214,12 @@ struct TechmapPass : public Pass {
log("\n");
log("A cell with the name _TECHMAP_REPLACE_ in the map file will inherit the name\n");
log("and attributes of the cell that is being replaced.\n");
log("A cell with a name of the form `_TECHMAP_REPLACE_.<suffix>` in the map file will\n");
log("be named thus but with the `_TECHMAP_REPLACE_' prefix substituted with the name\n");
log("of the cell being replaced.\n");
log("Similarly, a wire named in the form `_TECHMAP_REPLACE_.<suffix>` will cause a\n");
log("new wire alias to be created and named as above but with the `_TECHMAP_REPLACE_'\n");
log("prefix also substituted.\n");
log("\n");
log("See 'help extract' for a pass that does the opposite thing.\n");
log("\n");