Miodrag Milanovic
a5edbc8836
Update CI, windows-2019 is deprecated
2025-06-09 19:07:53 +02:00
Miodrag Milanovic
c16cc539d4
Next dev cycle
2025-06-09 08:12:26 +02:00
Miodrag Milanovic
db72ec3bde
Release version 0.54
2025-06-09 07:23:54 +02:00
N. Engelhardt
0b19f628e9
Merge pull request #5172 from YosysHQ/nak/reduce_warning_spam
2025-06-08 06:50:56 +00:00
N. Engelhardt
cb79e28046
Merge pull request #5159 from YosysHQ/krys/fixing_selections
2025-06-08 06:40:15 +00:00
github-actions[bot]
2a25d92413
Bump version
2025-06-07 00:24:11 +00:00
N. Engelhardt
3fe31294d6
disable warning for intentional use of deprecated function (to assert the feature isn't used any more)
2025-06-06 16:41:25 +02:00
N. Engelhardt
f22248f056
downgrade verific warnings about common coding styles
2025-06-06 16:30:50 +02:00
Emil J
f123c6f452
Merge pull request #5170 from YosysHQ/emil/revert-log_debug
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Revert log_debug back to macro from function
2025-06-06 16:29:45 +02:00
N. Engelhardt
f1dea78603
don't warn for every blackbox from verific
2025-06-06 15:37:42 +02:00
Emil J. Tywoniak
a16227b209
Revert "Change the implementation of log_debug in kernel/log.h from a macro function to a normal function."
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This reverts commit 15cfce061a
2025-06-06 15:14:40 +02:00
github-actions[bot]
50b63c6481
Bump version
2025-06-05 00:24:30 +00:00
Emil J
378add3723
Merge pull request #5163 from YosysHQ/emil/fix-single-bit-vector-leak
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simplify: fix single_bit_vector memory leak
2025-06-04 17:00:54 +02:00
George Rennie
0fcf5c080d
Merge pull request #5158 from georgerennie/george/task_inout
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read_verilog/astsimplify: copy inout ports in and out of functions/tasks
2025-06-04 14:23:08 +01:00
George Rennie
ab40403d90
Merge pull request #5154 from georgerennie/george/post_incdec_undo_fix
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read_verilog: fix -1 constant used to correct post increment/decrement
2025-06-04 14:22:32 +01:00
Emil J. Tywoniak
c37b7b3bf4
simplify: fix single_bit_vector memory leak
2025-06-04 10:32:03 +02:00
Emil J
c21cd300a0
Merge pull request #5109 from YosysHQ/emil/aiger-map-fix-outputs
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aiger: fix -map and -vmap
2025-06-02 15:07:19 +02:00
N. Engelhardt
1c742441db
Merge pull request #5150 from YosysHQ/krys/aiger_ordering
2025-06-02 13:06:36 +00:00
Lofty
169f04e634
Merge pull request #5155 from YosysHQ/lofty/codeowners
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CODEOWNERS: add myself for the ABC doc
2025-06-02 08:38:32 +01:00
github-actions[bot]
86282027c0
Bump version
2025-05-31 00:23:36 +00:00
George Rennie
97f51bb4b7
tests: add tests for task/function argument input/output copying
2025-05-31 01:21:06 +01:00
Krystine Sherwin
785cabcb0f
abc9_ops: Skip opt_expr in proc
2025-05-31 12:16:37 +12:00
George Rennie
45e8ff476e
read_verilog: copy inout ports in and out of functions/tasks
2025-05-31 01:09:03 +01:00
Krystine Sherwin
ab0e3cc05f
Proc: Use selections consistently
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All `proc_*` passes now use the same module and process for loops, using `design->all_selected_modules()` and `mod->selected_processes()` respectively.
This simplifies the code, and makes the couple `proc_*` passes that were ignoring boxed modules stop doing that (which seems to have been erroneous rather than intentional).
2025-05-31 12:04:42 +12:00
KrystalDelusion
545753cc5a
Merge pull request #5143 from YosysHQ/krys/typedef_struct_global
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SystemVerilog: Fix typedef struct in global space
2025-05-31 09:59:26 +12:00
Krystine Sherwin
aac562d36a
aiger.cc: Explicit unsorted-pool-as-LIFO
2025-05-31 09:55:00 +12:00
KrystalDelusion
06db8828b2
abc.rst: Clarify larger-but-slower
2025-05-31 09:10:27 +12:00
Lofty
e421a03d5a
CODEOWNERS: add myself for the ABC doc
2025-05-30 22:05:54 +01:00
George Rennie
3790be114f
tests: add tests for verilog pre/post increment/decrement in expressions
2025-05-30 14:38:25 +01:00
George Rennie
70291f0e49
read_verilog: fix -1 constant used to correct post increment/decrement
2025-05-30 14:38:25 +01:00
KrystalDelusion
d96d1e3630
Merge pull request #5153 from garytwong/typo-fix
2025-05-30 15:58:59 +12:00
Gary Wong
7a9d727bd0
docs: several small documentation fixes.
2025-05-29 21:26:28 -06:00
George Rennie
3ef4c91c31
Merge pull request #5148 from georgerennie/george/convertible_to_int_fix
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Fix convertible_to_int handling of 32 bit unsigned ints with MSB set.
2025-05-29 10:33:12 +01:00
Krystine Sherwin
0072a267cc
write_aiger: Add no-sort option
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Prevents sorting input/output bits so that they remain in the same order they were read in.
2025-05-29 16:20:16 +12:00
github-actions[bot]
e046e3cdbf
Bump version
2025-05-28 00:24:34 +00:00
Lofty
6d64e73fe7
Merge pull request #5149 from YosysHQ/lofty/abc_new-genlib
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Add genlib support to abc_new
2025-05-27 11:04:47 +01:00
Lofty
e4ab6acb46
Add genlib support to abc_new
2025-05-27 09:47:29 +01:00
github-actions[bot]
4f968c6695
Bump version
2025-05-27 00:24:03 +00:00
KrystalDelusion
489a12d6c1
Merge pull request #5141 from garytwong/unique-if
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Accept (and ignore) SystemVerilog unique/priority if.
2025-05-27 09:45:50 +12:00
gatecat
45a6940f40
cxxrtl: Add debug items for state with private names
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Signed-off-by: gatecat <gatecat@ds0.me>
2025-05-26 16:58:13 +02:00
George Rennie
e0c1e88f19
kernel: use try_as_int to implement as_int_compress
2025-05-26 15:34:13 +01:00
George Rennie
353fd0f7f4
tests: test opt_expr for 32 bit unsigned shifts
2025-05-26 15:28:44 +01:00
George Rennie
33a22b5cd1
kernel: fix convertible_to_int for overflowing unsigned values
2025-05-26 15:28:14 +01:00
Emil J
4f7ea38b49
Merge pull request #5127 from RonxBulld/refine_strip
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Disable STRIP operations when appropriate.
2025-05-26 15:03:34 +02:00
Krystine Sherwin
32ce23458f
read_verilog: Mark struct as custom type
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Being a custom type means that it will be resolved *before* (e.g.) a wire can use it as a type.
2025-05-26 12:19:33 +12:00
Krystine Sherwin
995a893afd
Tests: Add svtypes/typedef_struct_global.ys
2025-05-26 12:16:58 +12:00
Gary Wong
73e45d29d6
Add semantic test cases for SystemVerilog priority/unique/unique0 "if".
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The tests/verilog/*_if_enc.ys scripts instantiate simple encoder
modules, both with and without the SystemVerilog priority/unique/unique0
keywords, and check for consistency between the two for the subset
of inputs where the priority/unique/unique0 "if" result is
well-defined.
These tests vacuously succeed at the moment, since priority/unique
keywords are silently ignored and therefore the generated logic is
trivially identical. But the test cases will be capable of detecting
certain types of unsound optimisation if priority/unique handling is
introduced later.
2025-05-24 08:44:04 -06:00
github-actions[bot]
209df95fb9
Bump version
2025-05-24 00:23:33 +00:00
Emil J
18abf2d4f7
Merge pull request #5138 from YosysHQ/emil/libcache-verbose
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libcache: add -quiet and -verbose
2025-05-24 00:05:46 +02:00
Emil J
4b8d42d22c
Merge pull request #5095 from YosysHQ/emil/one-bit-width
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rtlil: enable single-bit vector wires
2025-05-23 15:55:45 +02:00
