mirror of
https://github.com/YosysHQ/yosys
synced 2025-06-06 14:13:23 +00:00
read_verilog: copy inout ports in and out of functions/tasks
This commit is contained in:
parent
4f7ea38b49
commit
45e8ff476e
1 changed files with 14 additions and 6 deletions
|
@ -4099,16 +4099,24 @@ skip_dynamic_range_lvalue_expansion:;
|
|||
delete arg;
|
||||
continue;
|
||||
}
|
||||
|
||||
AstNode *wire_id = new AstNode(AST_IDENTIFIER);
|
||||
wire_id->str = wire->str;
|
||||
AstNode *assign = child->is_input ?
|
||||
new AstNode(AST_ASSIGN_EQ, wire_id, arg) :
|
||||
new AstNode(AST_ASSIGN_EQ, arg, wire_id);
|
||||
assign->children[0]->was_checked = true;
|
||||
if (child->is_input)
|
||||
|
||||
if (child->is_input) {
|
||||
AstNode *assign = new AstNode(AST_ASSIGN_EQ, wire_id->clone(), arg->clone());
|
||||
assign->children[0]->was_checked = true;
|
||||
new_stmts.push_back(assign);
|
||||
else
|
||||
}
|
||||
|
||||
if (child->is_output) {
|
||||
AstNode *assign = new AstNode(AST_ASSIGN_EQ, arg->clone(), wire_id->clone());
|
||||
assign->children[0]->was_checked = true;
|
||||
output_assignments.push_back(assign);
|
||||
}
|
||||
|
||||
delete arg;
|
||||
delete wire_id;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue