Emil J. Tywoniak
7c73fd62e4
twine: fix replayability, reduce TwineSearch usage
2026-06-22 17:53:19 +02:00
Emil J. Tywoniak
bffe7a6e57
WIP migration to twine
2026-06-18 21:54:57 +02:00
Emil J. Tywoniak
0c450ce8c8
WIP migration to twine
2026-06-18 19:27:41 +02:00
Emil J. Tywoniak
3a5f5c77bf
twine: avoid TwinePool::lookup
2026-06-16 22:57:13 +02:00
Emil J. Tywoniak
dcc74755e7
WIP
2026-06-15 11:26:09 +02:00
Emil J. Tywoniak
d22805bd47
WIP
2026-06-12 16:25:07 +02:00
Emil J. Tywoniak
c3ffbf6fae
WIP
2026-06-12 00:18:53 +02:00
Emil J. Tywoniak
afdae7b87e
WIP
2026-06-11 20:02:02 +02:00
Emil J. Tywoniak
8e522b08c0
WIP
2026-06-11 13:17:54 +02:00
Emil J. Tywoniak
f592f2f3af
WIP
2026-06-10 19:22:53 +02:00
Emil J. Tywoniak
015ab4e45b
twine: start indexable colony with integer indices including preallocated twines
2026-06-10 14:54:48 +02:00
Emil J. Tywoniak
2117af318c
WIP
2026-06-10 14:54:48 +02:00
Emil J. Tywoniak
d13dfc21f4
WIP
2026-06-10 14:54:48 +02:00
Emil J. Tywoniak
1a8a95b472
rtlil: fix masquerade
2026-06-10 14:54:45 +02:00
Emil J. Tywoniak
2d3b7e9c92
rtlil: introduce ModuleNameMasq (KNOWN BROKEN, do not merge)
2026-06-10 14:54:43 +02:00
Emil J. Tywoniak
8f8a07efee
rtlil: replace AttrObject::meta_idx_ with ObjMeta pointer
2026-06-10 14:54:31 +02:00
Emil J. Tywoniak
0f31d3089e
rtlil: extend per-Design meta vector to hold name slot
2026-06-10 14:54:16 +02:00
Emil J. Tywoniak
f1edb571f2
rtlil: evacuate src_id_ from AttrObject to per-Design meta vector
2026-06-10 14:54:05 +02:00
Emil J. Tywoniak
e70eed3296
rtlil: add Module* back-pointer to RTLIL::Memory
2026-06-10 14:53:59 +02:00
Emil J. Tywoniak
9ed93e210b
rtlil: add per-Design src meta vector + freelist
2026-06-10 14:53:55 +02:00
Emil J. Tywoniak
29ab42bc4e
rtlil: add Module* back-pointer to inner-process AttrObjects
2026-06-10 14:53:48 +02:00
Emil J. Tywoniak
3424c00cd0
twine
2026-06-10 14:53:45 +02:00
Emil J. Tywoniak
c264649ae7
rtlil, patch: incremental signorm via connect_incremental, replacing batched sigNormalize in Patch::patch
2026-06-10 14:52:53 +02:00
Emil J. Tywoniak
5a6568edbe
rtlil, patch: update signorm index and driver fields when committing Cell from Patch to Design
2026-05-23 01:09:26 +02:00
Emil J. Tywoniak
9f22b9d2a0
patch: source transfer
2026-05-23 00:10:02 +02:00
Emil J. Tywoniak
dbc7e33908
rtlil: add CellAdderMixin for shared Cell adder interface between Module and Patch
2026-05-23 00:09:14 +02:00
Emil J. Tywoniak
6f0be1b4e9
rtlil: allow friends to use Wire constructors with a factory token pattern
2026-05-23 00:07:39 +02:00
Emil J. Tywoniak
3e6b740430
rtlil: allow friends to use Cell constructors with a factory token pattern
2026-05-23 00:07:39 +02:00
Emil J. Tywoniak
b3f605e0d2
patcher: start
2026-05-23 00:07:39 +02:00
Emil J. Tywoniak
b9eae3f64b
rtlil: publish signorm fanout
2026-05-22 18:41:49 +02:00
Emil J. Tywoniak
5dce475325
signorm: add timers
2026-05-22 18:40:16 +02:00
Emil J. Tywoniak
fb03a34277
rtlil: add dump_sigmap for hacky signorm debugging
2026-05-22 18:37:58 +02:00
Emil J. Tywoniak
6d08c53429
rtlil: forbid rewrite_sigspecs in signorm
2026-05-22 18:37:13 +02:00
Jannis Harder
423c8be71b
WIP half broken snapshot
2026-05-22 18:37:11 +02:00
Emil J. Tywoniak
10bbda93f7
rtlil: extend SigSpec::extract test
2026-04-24 11:04:19 +02:00
Emil J. Tywoniak
25b9b796c4
rtlil: complicate extract again for packing
2026-04-24 11:04:19 +02:00
Robert O'Callahan
b42bb05b63
Parallelize Design::check()
2026-03-06 02:03:21 +00:00
Robert O'Callahan
7af5dbae35
Add IdString::unescape() method
...
We've already talked about adding this as an alternative to `log_id()`, and we'll
need it later in this PR.
2026-03-06 02:03:21 +00:00
nella
04822c6660
Readd builtin_ff_cell_types for plugin parity.
2026-03-04 12:39:45 +01:00
nella
66bd4716cf
rtlil use newcelltypes.
2026-03-04 12:39:45 +01:00
Natalia
cf511628b0
modify generator for pyosys/wrappers.cc instead of headers
2026-01-18 02:11:09 -08:00
Natalia
fb864e91ee
Add Design::run_pass() API for programmatic pass execution
...
This commit adds a new run_pass() method to the RTLIL::Design class,
providing a convenient API for executing Yosys passes programmatically.
This is particularly useful for PyYosys users who want to run passes
on a design object without needing to manually construct Pass::call()
invocations. The method wraps Pass::call() with appropriate logging
to maintain consistency with command-line pass execution.
Example usage (from Python):
design = ys.Design()
# ... build or load design ...
design.run_pass("hierarchy")
design.run_pass("proc")
design.run_pass("opt")
Changes:
- kernel/rtlil.h: Add run_pass() method declaration
- kernel/rtlil.cc: Implement run_pass() method
- tests/unit/kernel/test_design_run_pass.cc: Add unit tests
2026-01-14 17:35:45 -08:00
nella
210b733555
Add rtlil string getters
2026-01-14 15:37:18 +01:00
Robert O'Callahan
8da919587d
Parallelize opt_merge.
...
I'm not sure why but this is actually faster than existing `opt_merge` even with
YOSYS_MAX_THREADS=1, for the jpeg synthesis test. 16.0s before, 15.5s after for
end-to-end synthesis.
2026-01-08 04:21:39 +00:00
Emil J
0ab967b036
Merge pull request #5564 from rocallahan/pass-fuzz
...
Add support for fuzz-test comparison of two passes intended to give identical RTLIL results
2026-01-06 20:07:31 +01:00
Robert O'Callahan
a6d696ba2b
Give IdString a default move constructor and make it a POD type.
...
Now that we're not refcounting `IdString`, it can use the default move constructor.
This lets us make `IdString` a POD type so it can be passed in registers
in the standard C++ ABI.
2025-12-30 22:35:14 +00:00
Robert O'Callahan
48cdb499f2
Remove IdString::id_string().
...
This was needed for the short time when `ID()` could return a value of `StaticIdString`.
That is no longer a problem.
2025-12-22 01:57:30 +00:00
Robert O'Callahan
46cb05c471
Pass IdString by value instead of by const reference.
...
When IdString refcounting was expensive, it made sense to pass it by const reference
instead of by value, to avoid refcount churn. Now that IdString is not refcounted,
it's slightly more efficient to pass it by value.
2025-12-22 01:52:59 +00:00
Robert O'Callahan
ddd6a16ee0
Add -legalize option to read_rtlil
2025-12-21 21:47:48 +00:00
Robert O'Callahan
b23dc345ae
Make it safe to access .c_str() for autoidx IDs in a multithreaded context
2025-11-25 22:49:41 +00:00
