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https://github.com/YosysHQ/yosys
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Add -legalize option to read_rtlil
This commit is contained in:
Robert O'Callahan
parent
914e14946d
commit
ddd6a16ee0
3 changed files with 131 additions and 20 deletions
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@ -40,6 +40,7 @@ struct RTLILFrontendWorker {
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bool flag_nooverwrite = false;
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bool flag_overwrite = false;
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bool flag_lib = false;
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bool flag_legalize = false;
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int line_num;
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std::string line_buf;
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@ -322,6 +323,17 @@ struct RTLILFrontendWorker {
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return val;
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}
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RTLIL::Wire *legalize_wire(RTLIL::IdString id)
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{
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int wires_size = current_module->wires_size();
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if (wires_size == 0)
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error("No wires found for legalization");
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int hash = hash_ops<RTLIL::IdString>::hash(id).yield();
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RTLIL::Wire *wire = current_module->wire_at(abs(hash % wires_size));
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log("Legalizing wire `%s' to `%s'.\n", log_id(id), log_id(wire->name));
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return wire;
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}
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RTLIL::SigSpec parse_sigspec()
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{
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RTLIL::SigSpec sig;
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@ -339,8 +351,12 @@ struct RTLILFrontendWorker {
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std::optional<RTLIL::IdString> id = try_parse_id();
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if (id.has_value()) {
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RTLIL::Wire *wire = current_module->wire(*id);
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if (wire == nullptr)
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error("Wire `%s' not found.", *id);
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if (wire == nullptr) {
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if (flag_legalize)
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wire = legalize_wire(*id);
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else
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error("Wire `%s' not found.", *id);
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}
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sig = RTLIL::SigSpec(wire);
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} else {
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sig = RTLIL::SigSpec(parse_const());
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@ -349,17 +365,44 @@ struct RTLILFrontendWorker {
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while (try_parse_char('[')) {
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int left = parse_integer();
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if (left >= sig.size() || left < 0)
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error("bit index %d out of range", left);
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if (left >= sig.size() || left < 0) {
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if (flag_legalize) {
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int legalized;
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if (sig.size() == 0)
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legalized = 0;
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else
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legalized = std::max(0, std::min(left, sig.size() - 1));
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log("Legalizing bit index %d to %d.\n", left, legalized);
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left = legalized;
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} else {
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error("bit index %d out of range", left);
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}
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}
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if (try_parse_char(':')) {
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int right = parse_integer();
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if (right < 0)
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error("bit index %d out of range", right);
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if (left < right)
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error("invalid slice [%d:%d]", left, right);
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sig = sig.extract(right, left-right+1);
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if (right < 0) {
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if (flag_legalize) {
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log("Legalizing bit index %d to %d.\n", right, 0);
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right = 0;
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} else
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error("bit index %d out of range", right);
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}
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if (left < right) {
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if (flag_legalize) {
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log("Legalizing bit index %d to %d.\n", left, right);
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left = right;
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} else
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error("invalid slice [%d:%d]", left, right);
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}
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if (flag_legalize && left >= sig.size())
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log("Legalizing slice %d:%d by igoring it\n", left, right);
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else
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sig = sig.extract(right, left - right + 1);
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} else {
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sig = sig.extract(left);
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if (flag_legalize && left >= sig.size())
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log("Legalizing slice %d by igoring it\n", left);
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else
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sig = sig.extract(left);
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}
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expect_char(']');
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}
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@ -476,8 +519,14 @@ struct RTLILFrontendWorker {
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{
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std::optional<RTLIL::IdString> id = try_parse_id();
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if (id.has_value()) {
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if (current_module->wire(*id) != nullptr)
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error("RTLIL error: redefinition of wire %s.", *id);
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if (current_module->wire(*id) != nullptr) {
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if (flag_legalize) {
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log("Legalizing redefinition of wire %s.\n", *id);
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pool<RTLIL::Wire*> wires = {current_module->wire(*id)};
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current_module->remove(wires);
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} else
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error("RTLIL error: redefinition of wire %s.", *id);
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}
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wire = current_module->addWire(std::move(*id));
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break;
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}
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@ -528,8 +577,13 @@ struct RTLILFrontendWorker {
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{
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std::optional<RTLIL::IdString> id = try_parse_id();
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if (id.has_value()) {
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if (current_module->memories.count(*id) != 0)
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error("RTLIL error: redefinition of memory %s.", *id);
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if (current_module->memories.count(*id) != 0) {
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if (flag_legalize) {
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log("Legalizing redefinition of memory %s.\n", *id);
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current_module->remove(current_module->memories.at(*id));
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} else
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error("RTLIL error: redefinition of memory %s.", *id);
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}
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memory->name = std::move(*id);
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break;
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}
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@ -551,14 +605,36 @@ struct RTLILFrontendWorker {
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expect_eol();
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}
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void legalize_width_parameter(RTLIL::Cell *cell, RTLIL::IdString port_name)
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{
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std::string width_param_name = port_name.str() + "_WIDTH";
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if (cell->parameters.count(width_param_name) == 0)
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return;
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RTLIL::Const ¶m = cell->parameters.at(width_param_name);
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if (param.as_int() != 0)
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return;
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cell->parameters[width_param_name] = RTLIL::Const(cell->getPort(port_name).size());
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}
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void parse_cell()
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{
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RTLIL::IdString cell_type = parse_id();
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RTLIL::IdString cell_name = parse_id();
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expect_eol();
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if (current_module->cell(cell_name) != nullptr)
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error("RTLIL error: redefinition of cell %s.", cell_name);
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if (current_module->cell(cell_name) != nullptr) {
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if (flag_legalize) {
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RTLIL::IdString new_name;
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int suffix = 1;
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do {
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new_name = RTLIL::IdString(cell_name.str() + "_" + std::to_string(suffix));
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++suffix;
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} while (current_module->cell(new_name) != nullptr);
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log("Legalizing redefinition of cell %s by renaming to %s.\n", cell_name, new_name);
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cell_name = new_name;
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} else
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error("RTLIL error: redefinition of cell %s.", cell_name);
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}
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RTLIL::Cell *cell = current_module->addCell(cell_name, cell_type);
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cell->attributes = std::move(attrbuf);
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@ -587,9 +663,15 @@ struct RTLILFrontendWorker {
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expect_eol();
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} else if (try_parse_keyword("connect")) {
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RTLIL::IdString port_name = parse_id();
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if (cell->hasPort(port_name))
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error("RTLIL error: redefinition of cell port %s.", port_name);
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if (cell->hasPort(port_name)) {
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if (flag_legalize)
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log("Legalizing redefinition of cell port %s.", port_name);
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else
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error("RTLIL error: redefinition of cell port %s.", port_name);
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}
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cell->setPort(std::move(port_name), parse_sigspec());
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if (flag_legalize)
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legalize_width_parameter(cell, port_name);
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expect_eol();
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} else if (try_parse_keyword("end")) {
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expect_eol();
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@ -606,6 +688,11 @@ struct RTLILFrontendWorker {
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error("dangling attribute");
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RTLIL::SigSpec s1 = parse_sigspec();
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RTLIL::SigSpec s2 = parse_sigspec();
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if (flag_legalize) {
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int min_size = std::min(s1.size(), s2.size());
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s1 = s1.extract(0, min_size);
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s2 = s2.extract(0, min_size);
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}
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current_module->connect(std::move(s1), std::move(s2));
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expect_eol();
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}
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@ -682,8 +769,13 @@ struct RTLILFrontendWorker {
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RTLIL::IdString proc_name = parse_id();
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expect_eol();
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if (current_module->processes.count(proc_name) != 0)
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error("RTLIL error: redefinition of process %s.", proc_name);
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if (current_module->processes.count(proc_name) != 0) {
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if (flag_legalize) {
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log("Legalizing redefinition of process %s.\n", proc_name);
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current_module->remove(current_module->processes.at(proc_name));
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} else
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error("RTLIL error: redefinition of process %s.", proc_name);
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}
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RTLIL::Process *proc = current_module->addProcess(std::move(proc_name));
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proc->attributes = std::move(attrbuf);
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@ -804,6 +896,11 @@ struct RTLILFrontend : public Frontend {
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log(" -lib\n");
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log(" only create empty blackbox modules\n");
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log("\n");
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log(" -legalize\n");
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log(" prevent semantic errors (e.g. reference to unknown wire, redefinition of wire/cell)\n");
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log(" by deterministically rewriting the input into something valid. Useful when using\n");
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log(" fuzzing to generate random but valid RTLIL.\n");
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log("\n");
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}
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void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
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{
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@ -828,6 +925,10 @@ struct RTLILFrontend : public Frontend {
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worker.flag_lib = true;
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continue;
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}
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if (arg == "-legalize") {
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worker.flag_legalize = true;
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continue;
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}
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break;
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}
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extra_args(f, filename, args, argidx);
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@ -3039,6 +3039,13 @@ void RTLIL::Module::remove(RTLIL::Cell *cell)
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}
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}
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void RTLIL::Module::remove(RTLIL::Memory *memory)
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{
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log_assert(memories.count(memory->name) != 0);
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memories.erase(memory->name);
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delete memory;
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}
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void RTLIL::Module::remove(RTLIL::Process *process)
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{
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log_assert(processes.count(process->name) != 0);
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@ -2139,6 +2139,8 @@ public:
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}
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RTLIL::ObjRange<RTLIL::Wire*> wires() { return RTLIL::ObjRange<RTLIL::Wire*>(&wires_, &refcount_wires_); }
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int wires_size() const { return wires_.size(); }
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RTLIL::Wire* wire_at(int index) const { return wires_.element(index)->second; }
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RTLIL::ObjRange<RTLIL::Cell*> cells() { return RTLIL::ObjRange<RTLIL::Cell*>(&cells_, &refcount_cells_); }
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void add(RTLIL::Binding *binding);
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@ -2146,6 +2148,7 @@ public:
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// Removing wires is expensive. If you have to remove wires, remove them all at once.
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void remove(const pool<RTLIL::Wire*> &wires);
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void remove(RTLIL::Cell *cell);
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void remove(RTLIL::Memory *memory);
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void remove(RTLIL::Process *process);
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void rename(RTLIL::Wire *wire, RTLIL::IdString new_name);
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