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Code Activity
13142 commits 122 branches 59 tags 72 MiB
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1758 commits

Author SHA1 Message Date
SergeyDegtyar
2ae7dec530 Add tests for Xilinx UG901 examples 2019-10-17 17:08:38 +02:00
Clifford Wolf
e84cedfae4 Use "(id)" instead of "id" for types as temporary hack 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-10-14 05:24:31 +02:00
Eddie Hung
3fb604c75d Revert "Add test that is expecting to fail" 
This reverts commit c28d4b8047.
 2019-10-08 12:41:26 -07:00
Eddie Hung
cfc181cba9
Merge pull request #1432 from YosysHQ/eddie/fix1427 
Refactor peepopt_dffmux and be sensitive to \init when trimming
 2019-10-08 12:38:29 -07:00
Eddie Hung
4c89a4e642
Merge pull request #1433 from YosysHQ/eddie/equiv_opt_async2sync 
async2sync to be called by equiv_opt only when -async2sync given
 2019-10-08 10:53:44 -07:00
Eddie Hung
5c68da4150 Missing 'accept' at end of ice40_wrapcarry, spotted by @cliffordwolf 2019-10-05 09:27:12 -07:00
Miodrag Milanovic
c0fa6f3e1a Split mux tests per type 2019-10-04 13:05:16 +02:00
Miodrag Milanovic
1b80489486 Split latch check 2019-10-04 13:00:09 +02:00
Miodrag Milanovic
2c3e140246 split rest od ff's 2019-10-04 12:51:45 +02:00
Miodrag Milanovic
3de7889d08 Separate check for ff's types 2019-10-04 12:48:27 +02:00
Miodrag Milanovic
286a272872 Cleaned tests 2019-10-04 12:42:06 +02:00
Miodrag Milanovic
f94dc2c072 Remove not needed tests 2019-10-04 12:41:41 +02:00
Miodrag Milanovic
ef417fb1b3 Merge branch 'SergeyDegtyar/efinix' of https://github.com/SergeyDegtyar/yosys into mmicko/efinix 2019-10-04 12:20:49 +02:00
Miodrag Milanovic
03a3deec43 Cleanup and formating 2019-10-04 11:09:59 +02:00
Miodrag Milanovic
a5844e3ceb split latches into separate checks 2019-10-04 11:08:42 +02:00
Miodrag Milanovic
3238ee7d35 check muxes per type 2019-10-04 11:04:18 +02:00
Miodrag Milanovic
91ad3ab717 check ff's separately 2019-10-04 11:00:49 +02:00
Miodrag Milanovic
3d3479b0af Cleanup top modules and not used defines 2019-10-04 10:57:47 +02:00
Miodrag Milanovic
1435b9bf97 remove alu test 2019-10-04 10:55:13 +02:00
Miodrag Milanovic
b932654964 Merge branch 'SergeyDegtyar/anlogic' of https://github.com/SergeyDegtyar/yosys into mmicko/anlogic 2019-10-04 10:52:16 +02:00
Miodrag Milanovic
7785f23719 Check latches type one by one 2019-10-04 10:31:51 +02:00
Miodrag Milanovic
3358b2f185 Removed top module where not needed 2019-10-04 09:53:54 +02:00
Miodrag Milanovic
3c40c81030 Test muxes synth one by one 2019-10-04 08:52:54 +02:00
Miodrag Milanovic
d6ef9b1a6b Cleaned verilog code from not used defines 2019-10-04 08:45:58 +02:00
Miodrag Milanovic
abb5a3a44d Check for MULT18X18D, since that is working now 2019-10-04 08:44:10 +02:00
Miodrag Milanovic
9e8175fc75 Check flops one by one 2019-10-04 08:42:29 +02:00
Miodrag Milanovic
d19f765a58 Removed alu and div_mod tests as agreed 2019-10-04 08:41:53 +02:00
Eddie Hung
045f344038 Use sat -tempinduct and comments for why equiv_opt not sufficient 2019-10-03 11:11:50 -07:00
Eddie Hung
bd5889640b Disable equiv check for ice40 latches 2019-10-03 10:45:53 -07:00
Eddie Hung
5d680590d6 Use equiv_opt -async2sync for xilinx 2019-10-03 10:30:33 -07:00
Clifford Wolf
0e05424885
Merge pull request #1422 from YosysHQ/eddie/aigmap_select 
Add -select option to aigmap
 2019-10-03 11:54:04 +02:00
David Shah
9b9d24f15b sv: Improve tests 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-03 09:54:45 +01:00
David Shah
abc155715d sv: Add test scripts for typedefs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-03 09:54:14 +01:00
David Shah
af25585170 sv: Add support for memories of a typedef 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-03 09:54:14 +01:00
David Shah
30d2326030 sv: Add support for memory typedefs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-03 09:54:14 +01:00
David Shah
e70e4afb60 sv: Fix typedefs in packages 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-03 09:54:14 +01:00
David Shah
c962951612 sv: Fix typedef parameters 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-03 09:54:14 +01:00
David Shah
f6b5e47e40 sv: Switch parser to glr, prep for typedef 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-03 09:54:14 +01:00
Eddie Hung
e9645c7fa7 Fix broken CI, check reset even for constants, trim rstmux 2019-10-02 21:26:26 -07:00
Eddie Hung
e4bd5aaebf Fix test 2019-10-02 18:12:25 -07:00
Eddie Hung
c6a55d948a Merge branch 'eddie/fix_sat_init' into eddie/fix1427 2019-10-02 18:07:38 -07:00
Eddie Hung
f6fabc8fda Update test 2019-10-02 18:03:45 -07:00
Eddie Hung
e730a595ee Add test 2019-10-02 18:01:41 -07:00
Eddie Hung
c28d4b8047 Add test that is expecting to fail 2019-10-02 14:52:40 -07:00
Eddie Hung
a4f2f7d23c Extend test with renaming cells with prefix too 2019-10-02 12:43:18 -07:00
Sergey
eb750670e3
run-test.sh Move $x at end of line. 2019-10-01 11:14:12 +03:00
Sergey
e092c4ae6b
Merge branch 'master' into SergeyDegtyar/efinix 2019-10-01 11:04:32 +03:00
Sergey
d99b1e3261
Merge branch 'master' into SergeyDegtyar/anlogic 2019-10-01 10:57:09 +03:00
Sergey
fc56459746
run-test.sh Move $x at end of line. 2019-10-01 10:55:34 +03:00
Eddie Hung
1caaf51492 equiv_opt with -assert 2019-09-30 19:54:59 -07:00