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Add test that is expecting to fail

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This commit is contained in:
Eddie Hung 2019-10-02 14:52:40 -07:00
parent 6028f5df1a
commit c28d4b8047
1 changed files with 20 additions and 0 deletions
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20
tests/sat/initval.ys
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@ -2,3 +2,23 @@ read_verilog -sv initval.v
proc;;
sat -seq 10 -prove-asserts
read_verilog <<EOT
module gold(input clk, input i, output reg [1:0] o);
initial o = 2'b10;
always @(posedge clk)
o[0] <= {i,i};
endmodule
module gate(input clk, input i, output reg [1:0] o);
initial o = 2'b10;
always @(posedge clk)
o[0] <= i;
always @*
o[1] <= o[0];
endmodule
EOT
proc
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -seq 1 -falsify -prove-asserts -show-ports miter