mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-23 00:55:32 +00:00
Use "(id)" instead of "id" for types as temporary hack
Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
commit
e84cedfae4
17 changed files with 315 additions and 20 deletions
3
tests/svtypes/.gitignore
vendored
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3
tests/svtypes/.gitignore
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/*.log
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/*.out
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/run-test.mk
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20
tests/svtypes/run-test.sh
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20
tests/svtypes/run-test.sh
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#!/usr/bin/env bash
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set -e
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{
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echo "all::"
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for x in *.ys; do
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echo "all:: run-$x"
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echo "run-$x:"
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echo " @echo 'Running $x..'"
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echo " @../../yosys -ql ${x%.ys}.log $x"
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done
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for x in *.sv; do
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if [ ! -f "${x%.sv}.ys" ]; then
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echo "all:: check-$x"
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echo "check-$x:"
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echo " @echo 'Checking $x..'"
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echo " @../../yosys -ql ${x%.sv}.log -p \"prep -top top; sat -verify -prove-asserts\" $x"
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fi
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done
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} > run-test.mk
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exec ${MAKE:-make} -f run-test.mk
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10
tests/svtypes/typedef_memory.sv
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10
tests/svtypes/typedef_memory.sv
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module top(input [3:0] addr, wdata, input clk, wen, output reg [3:0] rdata);
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typedef logic [3:0] ram16x4_t[0:15];
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(ram16x4_t) mem;
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always @(posedge clk) begin
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if (wen) mem[addr] <= wdata;
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rdata <= mem[addr];
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end
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endmodule
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3
tests/svtypes/typedef_memory.ys
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3
tests/svtypes/typedef_memory.ys
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@ -0,0 +1,3 @@
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read_verilog -sv typedef_memory.sv
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prep -top top
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select -assert-count 1 t:$mem r:SIZE=16 %i r:WIDTH=4 %i
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10
tests/svtypes/typedef_memory_2.sv
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10
tests/svtypes/typedef_memory_2.sv
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module top(input [3:0] addr, wdata, input clk, wen, output reg [3:0] rdata);
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typedef logic [3:0] nibble;
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(nibble) mem[0:15];
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always @(posedge clk) begin
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if (wen) mem[addr] <= wdata;
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rdata <= mem[addr];
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end
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endmodule
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4
tests/svtypes/typedef_memory_2.ys
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4
tests/svtypes/typedef_memory_2.ys
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@ -0,0 +1,4 @@
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read_verilog -sv typedef_memory_2.sv
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prep -top top
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dump
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select -assert-count 1 t:$mem r:SIZE=16 %i r:WIDTH=4 %i
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11
tests/svtypes/typedef_package.sv
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11
tests/svtypes/typedef_package.sv
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@ -0,0 +1,11 @@
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package pkg;
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typedef logic [7:0] uint8_t;
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endpackage
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module top;
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(* keep *) (pkg::uint8_t) a = 8'hAA;
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always @* assert(a == 8'hAA);
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endmodule
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22
tests/svtypes/typedef_param.sv
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22
tests/svtypes/typedef_param.sv
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`define STRINGIFY(x) `"x`"
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`define STATIC_ASSERT(x) if(!(x)) $error({"assert failed: ", `STRINGIFY(x)})
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module top;
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typedef logic [1:0] uint2_t;
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typedef logic signed [3:0] int4_t;
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typedef logic signed [7:0] int8_t;
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typedef (int8_t) char_t;
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parameter (uint2_t) int2 = 2'b10;
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localparam (int4_t) int4 = -1;
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localparam (int8_t) int8 = int4;
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localparam (char_t) ch = int8;
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`STATIC_ASSERT(int2 == 2'b10);
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`STATIC_ASSERT(int4 == 4'b1111);
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`STATIC_ASSERT(int8 == 8'b11111111);
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`STATIC_ASSERT(ch == 8'b11111111);
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endmodule
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23
tests/svtypes/typedef_scopes.sv
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23
tests/svtypes/typedef_scopes.sv
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typedef logic [3:0] outer_uint4_t;
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module top;
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(outer_uint4_t) u4_i = 8'hA5;
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always @(*) assert(u4_i == 4'h5);
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typedef logic [3:0] inner_type;
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(inner_type) inner_i1 = 8'h5A;
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always @(*) assert(inner_i1 == 4'hA);
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if (1) begin: genblock
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typedef logic [7:0] inner_type;
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(inner_type) inner_gb_i = 8'hA5;
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always @(*) assert(inner_gb_i == 8'hA5);
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end
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(inner_type) inner_i2 = 8'h42;
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always @(*) assert(inner_i2 == 4'h2);
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endmodule
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19
tests/svtypes/typedef_simple.sv
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19
tests/svtypes/typedef_simple.sv
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module top;
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typedef logic [1:0] uint2_t;
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typedef logic signed [3:0] int4_t;
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typedef logic signed [7:0] int8_t;
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typedef (int8_t) char_t;
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(* keep *) (uint2_t) int2 = 2'b10;
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(* keep *) (int4_t) int4 = -1;
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(* keep *) (int8_t) int8 = int4;
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(* keep *) (char_t) ch = int8;
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always @* assert(int2 == 2'b10);
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always @* assert(int4 == 4'b1111);
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always @* assert(int8 == 8'b11111111);
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always @* assert(ch == 8'b11111111);
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endmodule
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