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Use "(id)" instead of "id" for types as temporary hack

Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2019-10-14 05:24:31 +02:00
commit e84cedfae4
17 changed files with 315 additions and 20 deletions

3
tests/svtypes/.gitignore vendored Normal file
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/*.log
/*.out
/run-test.mk

20
tests/svtypes/run-test.sh Executable file
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#!/usr/bin/env bash
set -e
{
echo "all::"
for x in *.ys; do
echo "all:: run-$x"
echo "run-$x:"
echo " @echo 'Running $x..'"
echo " @../../yosys -ql ${x%.ys}.log $x"
done
for x in *.sv; do
if [ ! -f "${x%.sv}.ys" ]; then
echo "all:: check-$x"
echo "check-$x:"
echo " @echo 'Checking $x..'"
echo " @../../yosys -ql ${x%.sv}.log -p \"prep -top top; sat -verify -prove-asserts\" $x"
fi
done
} > run-test.mk
exec ${MAKE:-make} -f run-test.mk

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module top(input [3:0] addr, wdata, input clk, wen, output reg [3:0] rdata);
typedef logic [3:0] ram16x4_t[0:15];
(ram16x4_t) mem;
always @(posedge clk) begin
if (wen) mem[addr] <= wdata;
rdata <= mem[addr];
end
endmodule

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read_verilog -sv typedef_memory.sv
prep -top top
select -assert-count 1 t:$mem r:SIZE=16 %i r:WIDTH=4 %i

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module top(input [3:0] addr, wdata, input clk, wen, output reg [3:0] rdata);
typedef logic [3:0] nibble;
(nibble) mem[0:15];
always @(posedge clk) begin
if (wen) mem[addr] <= wdata;
rdata <= mem[addr];
end
endmodule

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read_verilog -sv typedef_memory_2.sv
prep -top top
dump
select -assert-count 1 t:$mem r:SIZE=16 %i r:WIDTH=4 %i

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package pkg;
typedef logic [7:0] uint8_t;
endpackage
module top;
(* keep *) (pkg::uint8_t) a = 8'hAA;
always @* assert(a == 8'hAA);
endmodule

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`define STRINGIFY(x) `"x`"
`define STATIC_ASSERT(x) if(!(x)) $error({"assert failed: ", `STRINGIFY(x)})
module top;
typedef logic [1:0] uint2_t;
typedef logic signed [3:0] int4_t;
typedef logic signed [7:0] int8_t;
typedef (int8_t) char_t;
parameter (uint2_t) int2 = 2'b10;
localparam (int4_t) int4 = -1;
localparam (int8_t) int8 = int4;
localparam (char_t) ch = int8;
`STATIC_ASSERT(int2 == 2'b10);
`STATIC_ASSERT(int4 == 4'b1111);
`STATIC_ASSERT(int8 == 8'b11111111);
`STATIC_ASSERT(ch == 8'b11111111);
endmodule

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typedef logic [3:0] outer_uint4_t;
module top;
(outer_uint4_t) u4_i = 8'hA5;
always @(*) assert(u4_i == 4'h5);
typedef logic [3:0] inner_type;
(inner_type) inner_i1 = 8'h5A;
always @(*) assert(inner_i1 == 4'hA);
if (1) begin: genblock
typedef logic [7:0] inner_type;
(inner_type) inner_gb_i = 8'hA5;
always @(*) assert(inner_gb_i == 8'hA5);
end
(inner_type) inner_i2 = 8'h42;
always @(*) assert(inner_i2 == 4'h2);
endmodule

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module top;
typedef logic [1:0] uint2_t;
typedef logic signed [3:0] int4_t;
typedef logic signed [7:0] int8_t;
typedef (int8_t) char_t;
(* keep *) (uint2_t) int2 = 2'b10;
(* keep *) (int4_t) int4 = -1;
(* keep *) (int8_t) int8 = int4;
(* keep *) (char_t) ch = int8;
always @* assert(int2 == 2'b10);
always @* assert(int4 == 4'b1111);
always @* assert(int8 == 8'b11111111);
always @* assert(ch == 8'b11111111);
endmodule