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Merge pull request #1433 from YosysHQ/eddie/equiv_opt_async2sync

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async2sync to be called by equiv_opt only when -async2sync given
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Eddie Hung 2019-10-08 10:53:44 -07:00 • committed by GitHub
commit 4c89a4e642
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3 changed files with 19 additions and 13 deletions
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9
tests/ice40/latches.ys
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@ -1,14 +1,11 @@
read_verilog latches.v
design -save read
proc
async2sync # converts latches to a 'sync' variant clocked by a 'super'-clock
flatten
synth_ice40
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
# Can't run any sort of equivalence check because latches are blown to LUTs
#equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load read
#design -load preopt
synth_ice40
cd top
select -assert-count 4 t:SB_LUT4

4
tests/xilinx/latches.ys
View file

@ -2,9 +2,7 @@ read_verilog latches.v
proc
flatten
equiv_opt -assert -run :prove -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
async2sync
equiv_opt -assert -run prove: -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load preopt
synth_xilinx