mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-07-24 21:27:00 +00:00
Code Activity

sv: Add support for memory typedefs

Browse source 
Signed-off-by: David Shah <dave@ds0.me>
This commit is contained in:
David Shah 2019-09-20 11:39:15 +01:00
parent e70e4afb60
commit 30d2326030
3 changed files with 44 additions and 3 deletions
Download patch file Download diff file Expand all files Collapse all files

10
tests/svtypes/typedef_memory.sv Normal file
View file

@ -0,0 +1,10 @@
module top(input [3:0] addr, wdata, input clk, wen, output reg [3:0] rdata);
typedef logic [3:0] ram16x4_t[0:15];
ram16x4_t mem;
always @(posedge clk) begin
if (wen) mem[addr] <= wdata;
rdata <= mem[addr];
end
endmodule