Miodrag Milanovic 7785f23719 Check latches type one by one		2019-10-04 10:31:51 +02:00
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aiger
arch
asicworld
bram
ecp5	Check latches type one by one	2019-10-04 10:31:51 +02:00
errors
fsm
hana
ice40	Merge pull request #1359 from YosysHQ/xc7dsp	2019-09-29 11:26:22 -07:00
liberty
lut
memories
opt	Add missing -assert to equiv_opt	2019-09-06 22:51:44 -07:00
opt_share
proc	proc_clean: fix order of switch insertion.	2019-08-19 16:44:23 +00:00
realmath
rpc	rpc: new frontend.	2019-09-30 15:53:11 +00:00
sat	Revert to using clean	2019-08-27 09:24:32 -07:00
share
simple	simple/peepopt.v tests to various/peepopt.ys with equiv_opt & select	2019-09-05 08:43:22 -07:00
simple_abc9	Revert "abc9 followed by clean otherwise netlist could be invalid for sim"	2019-09-05 08:25:09 -07:00
smv
sva
svinterfaces
techmap	Fix _TECHMAP_REMOVEINIT_ handling.	2019-09-27 18:34:12 +02:00
tools
unit
various	Merge pull request #1355 from YosysHQ/eddie/peepopt_dffmuxext	2019-09-18 12:40:08 -07:00
vloghtb
xilinx	Add latch test modified from #1363	2019-09-30 12:52:43 +02:00