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	split rest od ff's
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					 3 changed files with 18 additions and 31 deletions
				
			
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			@ -43,9 +43,6 @@ hierarchy -top ndffnr
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equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd ndffnr # Constrain all select calls below inside the top module
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select -assert-count 1 t:EFX_FF
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select -assert-count 1 t:EFX_GBUFCE
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select -assert-count 1 t:EFX_FF
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select -assert-count 1 t:EFX_GBUFCE
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select -assert-count 1 t:EFX_LUT4
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			@ -13,25 +13,3 @@ module dffe
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		if ( en )
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			q <= d;
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endmodule
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module top (
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input clk,
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input en,
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input a,
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output b,b1,
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);
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dff u_dff (
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        .clk (clk ),
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        .d (a ),
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        .q (b )
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    );
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dffe u_ndffe (
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        .clk (clk ),
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        .en (en),
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        .d (a ),
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        .q (b1 )
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    );
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endmodule
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			@ -1,12 +1,24 @@
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read_verilog dffs.v
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hierarchy -top top
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design -save read
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proc
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flatten
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hierarchy -top dff
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equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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cd dff # Constrain all select calls below inside the top module
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select -assert-count 1 t:EFX_FF
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select -assert-count 1 t:EFX_GBUFCE
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select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D
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design -load read
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proc
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hierarchy -top dffe
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equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd dffe # Constrain all select calls below inside the top module
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select -assert-count 1 t:EFX_FF
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select -assert-count 1 t:EFX_GBUFCE
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select -assert-count 2 t:EFX_FF
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select -assert-count 1 t:EFX_LUT4
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select -assert-none t:EFX_GBUFCE t:EFX_FF t:EFX_LUT4 %% t:* %D
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select -assert-none t:EFX_FF t:EFX_GBUFCE t:EFX_LUT4 %% t:* %D
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