Robert O'Callahan
9e523e2fd7
Work around std::reverse miscompilation with empty range
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This causes problems when compiling with fuzzing instrumenation enabled.
2026-02-05 18:58:17 +00:00
Robert O'Callahan
3b563b877e
Make log_error() work in a Multithreaded context.
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`log_error()` causes an exit so we don't have to try too hard here. The main
thing is to ensure that we normally are able to exit without causing a stack
overflow due to recursive asserts about not being in a `Multithreaded` context.
2026-02-05 18:58:17 +00:00
Robert O'Callahan
81fd03c6e4
Add IdString::unescape() method
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We've already talked about adding this as an alternative to `log_id()`, and we'll
need it later in this PR.
2026-02-05 18:58:17 +00:00
Emil J
8bbde80e02
Merge pull request #5631 from rocallahan/cleanup-compare-signals
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Clean up `compare_signals()` in `opt_clean`
2026-02-04 17:45:05 +01:00
Emil J
2aa0e1d009
Merge pull request #5629 from rocallahan/remove-zero-wires
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Avoid scanning entire module in `Module::remove()` if there are no wires to remove
2026-02-04 17:44:24 +01:00
Emil J
992e64342c
Merge pull request #5621 from rocallahan/remove-opt-sort
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Remove `Design::sort()` calls from optimization passes
2026-02-04 16:55:56 +01:00
Miodrag Milanović
776b4d06a6
Merge pull request #5669 from YosysHQ/release/v0.62
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Release version 0.62
2026-02-04 08:55:31 +01:00
Miodrag Milanovic
ddfa34d743
Next dev cycle
2026-02-04 08:54:38 +01:00
Robert O'Callahan
7326bb7d66
Only reuse ABC processes if we're using yosys-abc and it was built with ENABLE_READLINE
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(cherry picked from commit 5054fd17d7
2026-02-04 17:19:10 +13:00
Miodrag Milanovic
fc11754557
Release version 0.62
2026-02-03 12:09:24 +01:00
Miodrag Milanović
6dbe03f0f5
Merge pull request #5667 from Logikable/vhdl
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Guard vhdl_file::UNDEFINED behind VERIFIC_VHDL_SUPPORT.
2026-02-03 07:59:52 +01:00
github-actions[bot]
153ddc0c84
Bump version
2026-02-03 00:33:37 +00:00
Sean Luchen
224549fb88
Guard vhdl_file::UNDEFINED behind VERIFIC_VHDL_SUPPORT.
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Signed-off-by: Sean Luchen <seanluchen@google.com>
2026-02-02 15:26:03 -08:00
KrystalDelusion
414b1b6019
Merge pull request #5651 from rocallahan/abc-error-nonfatal
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Handle ABC nonfatal "Error:" messages
2026-02-03 08:55:05 +13:00
Emil J
59653da599
Merge pull request #5609 from nataliakokoromyti/upstream-design-run-pass
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Add Design::run_pass()
2026-02-02 19:30:18 +01:00
Miodrag Milanović
f5c8368f7a
Merge pull request #5662 from YosysHQ/update_abc
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Update ABC as per 2026-02-02
2026-02-02 13:44:56 +01:00
Miodrag Milanovic
b88d6588bc
Update ABC as per 2026-02-02
2026-02-02 11:25:57 +01:00
Miodrag Milanović
ac427a79b0
Merge pull request #5644 from nataliakokoromyti/upstream-linux-perf-unistd
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Add unistd header for Linux
2026-01-30 08:17:43 +01:00
Miodrag Milanović
382b28acbe
Merge pull request #5648 from YosysHQ/verific_moreopts
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verific: fixed -sv2017 option and added ability to set VHDL standard
2026-01-30 08:17:19 +01:00
Robert O'Callahan
9c56c93632
Add missing newlines to some 'log_error's
2026-01-30 01:52:19 +00:00
Robert O'Callahan
6af1b5b19c
Don't treat ABC 'Error:' output as indicating a fatal error, since these messages aren't necessarily fatal
2026-01-30 01:52:19 +00:00
github-actions[bot]
106f289e31
Bump version
2026-01-30 00:30:58 +00:00
KrystalDelusion
5a4ad6a6d0
Merge pull request #5640 from YosysHQ/krys/fix_mod.py
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Don't use `module mod_name(...)` style in cell libs
2026-01-30 11:40:07 +13:00
Emil J
a68fee1115
Merge pull request #5646 from rocallahan/debug-design_equal
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Dump module details when `design_equal` fails
2026-01-29 18:57:24 +01:00
Natalia
61b1c3c75a
use run_pass in ecp5 add/sub test
2026-01-29 02:42:23 -08:00
Natalia
7439d2489e
add assertion to run_pass test
2026-01-29 02:23:07 -08:00
Miodrag Milanovic
b70f527c67
verific: fixed -sv2017 option and added ability to set VHDL standard if applicable
2026-01-29 10:32:30 +01:00
Miodrag Milanović
6ba8f3dc19
Merge pull request #5647 from YosysHQ/update_abc
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ABC update (MINGW fix)
2026-01-29 10:12:25 +01:00
Miodrag Milanović
43db5c9488
Merge pull request #5645 from nataliakokoromyti/upstream-verific-mixed-sv-vhdl
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Upstream verific mixed sv vhdl
2026-01-29 10:12:09 +01:00
Miodrag Milanovic
6007b68e9c
ABC update (MINGW fix)
2026-01-29 09:30:12 +01:00
Natalia
8d504ecb48
verific: use MFCU for SV file list
2026-01-29 00:03:28 -08:00
Natalia
b6c148f84a
tests/verific: ensure mixed -f requires VHDL unit
2026-01-28 22:46:10 -08:00
github-actions[bot]
1f6a13dac7
Bump version
2026-01-29 00:31:03 +00:00
Robert O'Callahan
139c38ecfa
Dump module details when design_equal fails
2026-01-28 18:32:12 +00:00
nella
8f6c4d40e4
Merge pull request #5623 from YosysHQ/nella/opt-dff-rewrite
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opt_dff restructure.
2026-01-28 14:41:40 +01:00
Natalia
5a64fe2d91
tests/verific: assert module count explicitly
2026-01-28 04:21:13 -08:00
Natalia
8c2ef89732
tests/verific: import mixed -f list with -all
2026-01-28 04:13:04 -08:00
Natalia
74c601db0f
tests/verific: add mixed -f list case
2026-01-28 03:55:42 -08:00
Natalia
6a6e5f0f54
linux_perf: only include unistd on Linux
2026-01-28 03:44:33 -08:00
Natalia
188082551a
verific: only use MFCU when VHDL present
2026-01-28 03:37:08 -08:00
Natalia
fc2b7c317f
linux_perf: include unistd for POSIX I/O
2026-01-28 03:14:20 -08:00
Emil J
75008b70e5
Merge pull request #5638 from YosysHQ/emil/linux_perf-fix-help
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linux_perf: mark internal, fix help formatting
2026-01-28 11:06:08 +01:00
Miodrag Milanović
97366933b3
Merge pull request #5643 from YosysHQ/update_abc
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Update ABC as per 2026-01-28
2026-01-28 10:21:08 +01:00
Miodrag Milanovic
fdff3dac2b
Update ABC as per 2026-01-28
2026-01-28 09:38:33 +01:00
Krystine Sherwin
8ed7ac04d8
linux_perf.cc: Fix overlength codeblock
2026-01-28 08:17:56 +13:00
Krystine Sherwin
4031310ebb
linux_perf.cc: Use formatted_help
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Gets the codeblock formatting better.
Also fold the on|off into a single usage.
2026-01-28 08:10:31 +13:00
Krystine Sherwin
aaebce7adc
log_help: Don't reformat codeblocks
2026-01-28 08:07:44 +13:00
Krystine Sherwin
c3ffb48a6b
Add and use fix_mod.py
2026-01-28 07:45:58 +13:00
github-actions[bot]
33e4b1d97f
Bump version
2026-01-27 00:28:42 +00:00
Gus Smith
09ceadfde7
Merge pull request #4269 from povik/icells_not_derived
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Avoid `module_not_derived` on internal cells in techmap result
2026-01-26 14:48:40 -08:00
