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Add and use fix_mod.py

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Krystine Sherwin 2026-01-28 07:45:58 +13:00
parent 33e4b1d97f
commit c3ffb48a6b
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10 changed files with 1803 additions and 725 deletions
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47
techlibs/fix_mod.py Normal file
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@ -0,0 +1,47 @@
import sys
import subprocess
import re
import os
def main():
script = sys.argv.pop(0)
try:
verilog, yosys = sys.argv
except ValueError:
print(f"Expected to be called as 'python3 {script} <cells_file> <yosys>'.")
exit(1)
proc = subprocess.run([yosys, '-p', f'read_verilog -lib {verilog}; write_verilog -blackboxes -'], stdout=subprocess.PIPE)
modules = {}
in_mod = False
mod = ""
decl = ""
for line in proc.stdout.decode('utf-8').splitlines(keepends=True):
m = re.match(r'(module (\S+)\(.+)', line, re.S)
if m:
decl, mod = m.groups()
in_mod = True
elif in_mod:
decl += line
if in_mod and decl.rstrip()[-1] == ';':
in_mod = False
modules[mod] = decl
src = f'{verilog}.tmp'
os.rename(verilog, src)
dest = verilog
with open(dest, 'w') as f_out:
with open(src, 'r') as f_in:
for line in f_in:
m = re.match(r'module (\S+) \(\.\.\.\)', line)
if m:
line = modules[m.group(1)]
print(line, end='', file=f_out)
if src.endswith('.tmp'):
os.remove(src)
if __name__ == "__main__":
main()

106
techlibs/gowin/cells_xtra_gw1n.v
View file

@ -1,41 +1,41 @@
// Created by cells_xtra.py
module LUT5 (...);
module LUT5(I0, I1, I2, I3, I4, F);
parameter INIT = 32'h00000000;
input I0, I1, I2, I3, I4;
output F;
endmodule
module LUT6 (...);
module LUT6(I0, I1, I2, I3, I4, I5, F);
parameter INIT = 64'h0000_0000_0000_0000;
input I0, I1, I2, I3, I4, I5;
output F;
endmodule
module LUT7 (...);
module LUT7(I0, I1, I2, I3, I4, I5, I6, F);
parameter INIT = 128'h0000_0000_0000_0000_0000_0000_0000_0000;
input I0, I1, I2, I3, I4, I5, I6;
output F;
endmodule
module LUT8 (...);
module LUT8(I0, I1, I2, I3, I4, I5, I6, I7, F);
parameter INIT = 256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000;
input I0, I1, I2, I3, I4, I5, I6, I7;
output F;
endmodule
module INV (...);
module INV(I, O);
input I;
output O;
endmodule
module IODELAY (...);
module IODELAY(DI, SDTAP, SETN, VALUE, DF, DO);
parameter C_STATIC_DLY = 0;
input DI;
input SDTAP;
@ -46,7 +46,7 @@ output DO;
endmodule
module IEM (...);
module IEM(D, CLK, RESET, MCLK, LAG, LEAD);
parameter WINSIZE = "SMALL";
parameter GSREN = "false";
parameter LSREN = "true";
@ -55,14 +55,14 @@ output LAG, LEAD;
endmodule
module ROM16 (...);
module ROM16(AD, DO);
parameter INIT_0 = 16'h0000;
input [3:0] AD;
output DO;
endmodule
module ROM (...);
module ROM(CLK, CE, OCE, RESET, WRE, AD, BLKSEL, DO);
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH = 32;
parameter BLK_SEL = 3'b000;
@ -141,7 +141,7 @@ output [31:0] DO;
endmodule
module ROMX9 (...);
module ROMX9(CLK, CE, OCE, RESET, WRE, AD, BLKSEL, DO);
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH = 36;
parameter BLK_SEL = 3'b000;
@ -220,7 +220,7 @@ output [35:0] DO;
endmodule
module pROM (...);
module pROM(CLK, CE, OCE, RESET, AD, DO);
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH = 32;
parameter RESET_MODE = "SYNC";
@ -296,7 +296,7 @@ output [31:0] DO;
endmodule
module pROMX9 (...);
module pROMX9(CLK, CE, OCE, RESET, AD, DO);
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH = 36;
parameter RESET_MODE = "SYNC";
@ -372,7 +372,7 @@ output [35:0] DO;
endmodule
module SDPB (...);
module SDPB(CLKA, CEA, CLKB, CEB, OCE, RESETA, RESETB, ADA, ADB, DI, BLKSELA, BLKSELB, DO);
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH_0 = 32;
parameter BIT_WIDTH_1 = 32;
@ -453,7 +453,7 @@ output [31:0] DO;
endmodule
module SDPX9B (...);
module SDPX9B(CLKA, CEA, CLKB, CEB, OCE, RESETA, RESETB, ADA, ADB, BLKSELA, BLKSELB, DI, DO);
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH_0 = 36;
parameter BIT_WIDTH_1 = 36;
@ -534,7 +534,7 @@ output [35:0] DO;
endmodule
module DPB (...);
module DPB(CLKA, CEA, CLKB, CEB, OCEA, OCEB, RESETA, RESETB, WREA, WREB, ADA, ADB, BLKSELA, BLKSELB, DIA, DIB, DOA, DOB);
parameter READ_MODE0 = 1'b0;
parameter READ_MODE1 = 1'b0;
parameter WRITE_MODE0 = 2'b00;
@ -619,7 +619,7 @@ output [15:0] DOA, DOB;
endmodule
module DPX9B (...);
module DPX9B(CLKA, CEA, CLKB, CEB, OCEA, OCEB, RESETA, RESETB, WREA, WREB, ADA, ADB, DIA, DIB, BLKSELA, BLKSELB, DOA, DOB);
parameter READ_MODE0 = 1'b0;
parameter READ_MODE1 = 1'b0;
parameter WRITE_MODE0 = 2'b00;
@ -704,7 +704,7 @@ output [17:0] DOA, DOB;
endmodule
module PADD18 (...);
module PADD18(A, B, ASEL, CE, CLK, RESET, SI, SBI, SO, SBO, DOUT);
input [17:0] A;
input [17:0] B;
input ASEL;
@ -720,7 +720,7 @@ parameter BSEL_MODE = 1'b1;
parameter SOREG = 1'b0;
endmodule
module PADD9 (...);
module PADD9(A, B, ASEL, CE, CLK, RESET, SI, SBI, SO, SBO, DOUT);
input [8:0] A;
input [8:0] B;
input ASEL;
@ -736,7 +736,7 @@ parameter BSEL_MODE = 1'b1;
parameter SOREG = 1'b0;
endmodule
module MULT9X9 (...);
module MULT9X9(A, SIA, B, SIB, ASIGN, BSIGN, ASEL, BSEL, CE, CLK, RESET, DOUT, SOA, SOB);
input [8:0] A,SIA;
input [8:0] B,SIB;
input ASIGN,BSIGN;
@ -756,7 +756,7 @@ parameter SOA_REG = 1'b0;
parameter MULT_RESET_MODE = "SYNC";
endmodule
module MULT18X18 (...);
module MULT18X18(A, SIA, B, SIB, ASIGN, BSIGN, ASEL, BSEL, CE, CLK, RESET, DOUT, SOA, SOB);
input [17:0] A,SIA;
input [17:0] B,SIB;
input ASIGN,BSIGN;
@ -776,7 +776,7 @@ parameter SOA_REG = 1'b0;
parameter MULT_RESET_MODE = "SYNC";
endmodule
module MULT36X36 (...);
module MULT36X36(A, B, ASIGN, BSIGN, CE, CLK, RESET, DOUT);
input [35:0] A;
input [35:0] B;
input ASIGN,BSIGN;
@ -794,7 +794,7 @@ parameter BSIGN_REG = 1'b0;
parameter MULT_RESET_MODE = "SYNC";
endmodule
module MULTALU36X18 (...);
module MULTALU36X18(A, B, C, ASIGN, BSIGN, ACCLOAD, CE, CLK, RESET, CASI, DOUT, CASO);
input [17:0] A;
input [35:0] B;
input [53:0] C;
@ -819,7 +819,7 @@ parameter MULTALU36X18_MODE = 0;
parameter C_ADD_SUB = 1'b0;
endmodule
module MULTADDALU18X18 (...);
module MULTADDALU18X18(A0, B0, A1, B1, C, SIA, SIB, ASIGN, BSIGN, ASEL, BSEL, CASI, CE, CLK, RESET, ACCLOAD, DOUT, CASO, SOA, SOB);
input [17:0] A0;
input [17:0] B0;
input [17:0] A1;
@ -857,7 +857,7 @@ parameter MULTADDALU18X18_MODE = 0;
parameter MULT_RESET_MODE = "SYNC";
endmodule
module MULTALU18X18 (...);
module MULTALU18X18(A, B, CLK, CE, RESET, ASIGN, BSIGN, ACCLOAD, DSIGN, C, D, CASI, DOUT, CASO);
input [17:0] A, B;
input CLK,CE,RESET;
input ASIGN, BSIGN;
@ -883,7 +883,7 @@ parameter C_ADD_SUB = 1'b0;
parameter MULTALU18X18_MODE = 0;
endmodule
module ALU54D (...);
module ALU54D(A, B, ASIGN, BSIGN, ACCLOAD, CASI, CLK, CE, RESET, DOUT, CASO);
input [53:0] A, B;
input ASIGN,BSIGN;
input ACCLOAD;
@ -903,19 +903,19 @@ parameter ALUD_MODE = 0;
parameter ALU_RESET_MODE = "SYNC";
endmodule
module BUFG (...);
module BUFG(O, I);
output O;
input I;
endmodule
module BUFS (...);
module BUFS(O, I);
output O;
input I;
endmodule
module PLL (...);
module PLL(CLKIN, CLKFB, RESET, RESET_P, RESET_I, RESET_S, FBDSEL, IDSEL, ODSEL, PSDA, FDLY, DUTYDA, CLKOUT, LOCK, CLKOUTP, CLKOUTD, CLKOUTD3);
input CLKIN;
input CLKFB;
input RESET;
@ -956,39 +956,39 @@ parameter CLKOUTD3_SRC = "CLKOUT";
parameter DEVICE = "GW1N-4";
endmodule
module TLVDS_IBUF (...);
module TLVDS_IBUF(O, I, IB);
output O;
input I, IB;
endmodule
module TLVDS_TBUF (...);
module TLVDS_TBUF(O, OB, I, OEN);
output O, OB;
input I, OEN;
endmodule
module TLVDS_IOBUF (...);
module TLVDS_IOBUF(O, IO, IOB, I, OEN);
output O;
inout IO, IOB;
input I, OEN;
endmodule
module ELVDS_IBUF (...);
module ELVDS_IBUF(O, I, IB);
output O;
input I, IB;
endmodule
module ELVDS_TBUF (...);
module ELVDS_TBUF(O, OB, I, OEN);
output O, OB;
input I, OEN;
endmodule
module ELVDS_IOBUF (...);
module ELVDS_IOBUF(O, IO, IOB, I, OEN);
output O;
inout IO, IOB;
input I, OEN;
endmodule
module MIPI_IBUF (...);
module MIPI_IBUF(OH, OL, OB, IO, IOB, I, IB, OEN, OENB, HSREN);
output OH, OL, OB;
inout IO, IOB;
input I, IB;
@ -996,40 +996,40 @@ input OEN, OENB;
input HSREN;
endmodule
module MIPI_IBUF_HS (...);
module MIPI_IBUF_HS(OH, I, IB);
output OH;
input I, IB;
endmodule
module MIPI_IBUF_LP (...);
module MIPI_IBUF_LP(OL, OB, I, IB);
output OL;
output OB;
input I;
input IB;
endmodule
module MIPI_OBUF (...);
module MIPI_OBUF(O, OB, I, IB, MODESEL);
output O, OB;
input I, IB, MODESEL;
endmodule
module MIPI_OBUF_A (...);
module MIPI_OBUF_A(O, OB, I, IB, IL, MODESEL);
output O, OB;
input I, IB, IL, MODESEL;
endmodule
module ELVDS_IBUF_MIPI (...);
module ELVDS_IBUF_MIPI(OH, OL, I, IB);
output OH, OL;
input I, IB;
endmodule
module I3C_IOBUF (...);
module I3C_IOBUF(O, IO, I, MODESEL);
output O;
inout IO;
input I, MODESEL;
endmodule
module CLKDIV (...);
module CLKDIV(HCLKIN, RESETN, CALIB, CLKOUT);
input HCLKIN;
input RESETN;
input CALIB;
@ -1038,12 +1038,12 @@ parameter DIV_MODE = "2";
parameter GSREN = "false";
endmodule
module DHCEN (...);
module DHCEN(CLKIN, CE, CLKOUT);
input CLKIN,CE;
output CLKOUT;
endmodule
module DLLDLY (...);
module DLLDLY(CLKIN, DLLSTEP, DIR, LOADN, MOVE, CLKOUT, FLAG);
input CLKIN;
input [7:0] DLLSTEP;
input DIR,LOADN,MOVE;
@ -1054,7 +1054,7 @@ parameter DLY_SIGN = 1'b0;
parameter DLY_ADJ = 0;
endmodule
module FLASH96K (...);
module FLASH96K(RA, CA, PA, MODE, SEQ, ACLK, PW, RESET, PE, OE, RMODE, WMODE, RBYTESEL, WBYTESEL, DIN, DOUT);
input [5:0] RA,CA,PA;
input [3:0] MODE;
input [1:0] SEQ;
@ -1065,7 +1065,7 @@ input [31:0] DIN;
output [31:0] DOUT;
endmodule
module FLASH256K (...);
module FLASH256K(XADR, YADR, XE, YE, SE, ERASE, PROG, NVSTR, DIN, DOUT);
input[6:0]XADR;
input[5:0]YADR;
input XE,YE,SE;
@ -1087,7 +1087,7 @@ parameter IDLE = 4'd0,
RD_S2 = 4'd12;
endmodule
module FLASH608K (...);
module FLASH608K(XADR, YADR, XE, YE, SE, ERASE, PROG, NVSTR, DIN, DOUT);
input[8:0]XADR;
input[5:0]YADR;
input XE,YE,SE;
@ -1109,31 +1109,31 @@ parameter IDLE = 4'd0,
RD_S2 = 4'd12;
endmodule
module DCS (...);
module DCS(CLK0, CLK1, CLK2, CLK3, SELFORCE, CLKSEL, CLKOUT);
input CLK0, CLK1, CLK2, CLK3, SELFORCE;
input [3:0] CLKSEL;
output CLKOUT;
parameter DCS_MODE = "RISING";
endmodule
module DQCE (...);
module DQCE(CLKIN, CE, CLKOUT);
input CLKIN;
input CE;
output CLKOUT;
endmodule
module CLKDIV2 (...);
module CLKDIV2(HCLKIN, RESETN, CLKOUT);
parameter GSREN = "false";
input HCLKIN, RESETN;
output CLKOUT;
endmodule
module DHCENC (...);
module DHCENC(CLKIN, CE, CLKOUT, CLKOUTN);
input CLKIN, CE;
output CLKOUT, CLKOUTN;
endmodule
module FLASH64K (...);
module FLASH64K(XADR, YADR, XE, YE, SE, ERASE, PROG, NVSTR, SLEEP, DIN, DOUT);
input[4:0]XADR;
input[5:0]YADR;
input XE,YE,SE;
@ -1156,7 +1156,7 @@ parameter IDLE = 4'd0,
RD_S2 = 4'd12;
endmodule
module FLASH64KZ (...);
module FLASH64KZ(XADR, YADR, XE, YE, SE, ERASE, PROG, NVSTR, DIN, DOUT);
input[4:0]XADR;
input[5:0]YADR;
input XE,YE,SE;

113
techlibs/gowin/cells_xtra_gw2a.v
View file

@ -1,41 +1,41 @@
// Created by cells_xtra.py
module LUT5 (...);
module LUT5(I0, I1, I2, I3, I4, F);
parameter INIT = 32'h00000000;
input I0, I1, I2, I3, I4;
output F;
endmodule
module LUT6 (...);
module LUT6(I0, I1, I2, I3, I4, I5, F);
parameter INIT = 64'h0000_0000_0000_0000;
input I0, I1, I2, I3, I4, I5;
output F;
endmodule
module LUT7 (...);
module LUT7(I0, I1, I2, I3, I4, I5, I6, F);
parameter INIT = 128'h0000_0000_0000_0000_0000_0000_0000_0000;
input I0, I1, I2, I3, I4, I5, I6;
output F;
endmodule
module LUT8 (...);
module LUT8(I0, I1, I2, I3, I4, I5, I6, I7, F);
parameter INIT = 256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000;
input I0, I1, I2, I3, I4, I5, I6, I7;
output F;
endmodule
module INV (...);
module INV(I, O);
input I;
output O;
endmodule
module IDDR_MEM (...);
module IDDR_MEM(D, ICLK, PCLK, WADDR, RADDR, RESET, Q0, Q1);
parameter GSREN = "false";
parameter LSREN = "true";
input D, ICLK, PCLK;
@ -46,7 +46,7 @@ output Q0,Q1;
endmodule
module ODDR_MEM (...);
module ODDR_MEM(D0, D1, TX, PCLK, TCLK, RESET, Q0, Q1);
parameter GSREN = "false";
parameter LSREN = "true";
parameter TCLK_SOURCE = "DQSW";
@ -57,7 +57,7 @@ output Q0, Q1;
endmodule
module IDES4_MEM (...);
module IDES4_MEM(D, ICLK, FCLK, PCLK, WADDR, RADDR, RESET, CALIB, Q0, Q1, Q2, Q3);
parameter GSREN = "false";
parameter LSREN = "true";
input D, ICLK, FCLK, PCLK;
@ -68,7 +68,7 @@ output Q0,Q1,Q2,Q3;
endmodule
module IDES8_MEM (...);
module IDES8_MEM(D, ICLK, FCLK, PCLK, WADDR, RADDR, RESET, CALIB, Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7);
parameter GSREN = "false";
parameter LSREN = "true";
input D, ICLK, FCLK, PCLK;
@ -79,7 +79,7 @@ output Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7;
endmodule
module OSER4_MEM (...);
module OSER4_MEM(D0, D1, D2, D3, TX0, TX1, PCLK, FCLK, TCLK, RESET, Q0, Q1);
parameter GSREN = "false";
parameter LSREN = "true";
parameter HWL = "false";
@ -92,7 +92,7 @@ output Q0, Q1;
endmodule
module OSER8_MEM (...);
module OSER8_MEM(D0, D1, D2, D3, D4, D5, D6, D7, TX0, TX1, TX2, TX3, PCLK, FCLK, TCLK, RESET, Q0, Q1);
parameter GSREN = "false";
parameter LSREN = "true";
parameter HWL = "false";
@ -105,7 +105,7 @@ output Q0, Q1;
endmodule
module IODELAY (...);
module IODELAY(DI, SDTAP, SETN, VALUE, DF, DO);
parameter C_STATIC_DLY = 0;
input DI;
input SDTAP;
@ -116,7 +116,7 @@ output DO;
endmodule
module IEM (...);
module IEM(D, CLK, RESET, MCLK, LAG, LEAD);
parameter WINSIZE = "SMALL";
parameter GSREN = "false";
parameter LSREN = "true";
@ -125,14 +125,14 @@ output LAG, LEAD;
endmodule
module ROM16 (...);
module ROM16(AD, DO);
parameter INIT_0 = 16'h0000;
input [3:0] AD;
output DO;
endmodule
module ROM (...);
module ROM(CLK, CE, OCE, RESET, WRE, AD, BLKSEL, DO);
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH = 32;
parameter BLK_SEL = 3'b000;
@ -211,7 +211,7 @@ output [31:0] DO;
endmodule
module ROMX9 (...);
module ROMX9(CLK, CE, OCE, RESET, WRE, AD, BLKSEL, DO);
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH = 36;
parameter BLK_SEL = 3'b000;
@ -290,7 +290,7 @@ output [35:0] DO;
endmodule
module pROM (...);
module pROM(CLK, CE, OCE, RESET, AD, DO);
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH = 32;
parameter RESET_MODE = "SYNC";
@ -366,7 +366,7 @@ output [31:0] DO;
endmodule
module pROMX9 (...);
module pROMX9(CLK, CE, OCE, RESET, AD, DO);
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH = 36;
parameter RESET_MODE = "SYNC";
@ -442,7 +442,7 @@ output [35:0] DO;
endmodule
module SDPB (...);
module SDPB(CLKA, CEA, CLKB, CEB, OCE, RESETA, RESETB, ADA, ADB, DI, BLKSELA, BLKSELB, DO);
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH_0 = 32;
parameter BIT_WIDTH_1 = 32;
@ -523,7 +523,7 @@ output [31:0] DO;
endmodule
module SDPX9B (...);
module SDPX9B(CLKA, CEA, CLKB, CEB, OCE, RESETA, RESETB, ADA, ADB, BLKSELA, BLKSELB, DI, DO);
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH_0 = 36;
parameter BIT_WIDTH_1 = 36;
@ -604,7 +604,7 @@ output [35:0] DO;
endmodule
module DPB (...);
module DPB(CLKA, CEA, CLKB, CEB, OCEA, OCEB, RESETA, RESETB, WREA, WREB, ADA, ADB, BLKSELA, BLKSELB, DIA, DIB, DOA, DOB);
parameter READ_MODE0 = 1'b0;
parameter READ_MODE1 = 1'b0;
parameter WRITE_MODE0 = 2'b00;
@ -689,7 +689,7 @@ output [15:0] DOA, DOB;
endmodule
module DPX9B (...);
module DPX9B(CLKA, CEA, CLKB, CEB, OCEA, OCEB, RESETA, RESETB, WREA, WREB, ADA, ADB, DIA, DIB, BLKSELA, BLKSELB, DOA, DOB);
parameter READ_MODE0 = 1'b0;
parameter READ_MODE1 = 1'b0;
parameter WRITE_MODE0 = 2'b00;
@ -774,7 +774,7 @@ output [17:0] DOA, DOB;
endmodule
module PADD18 (...);
module PADD18(A, B, ASEL, CE, CLK, RESET, SI, SBI, SO, SBO, DOUT);
input [17:0] A;
input [17:0] B;
input ASEL;
@ -790,7 +790,7 @@ parameter BSEL_MODE = 1'b1;
parameter SOREG = 1'b0;
endmodule
module PADD9 (...);
module PADD9(A, B, ASEL, CE, CLK, RESET, SI, SBI, SO, SBO, DOUT);
input [8:0] A;
input [8:0] B;
input ASEL;
@ -806,7 +806,7 @@ parameter BSEL_MODE = 1'b1;
parameter SOREG = 1'b0;
endmodule
module MULT9X9 (...);
module MULT9X9(A, SIA, B, SIB, ASIGN, BSIGN, ASEL, BSEL, CE, CLK, RESET, DOUT, SOA, SOB);
input [8:0] A,SIA;
input [8:0] B,SIB;
input ASIGN,BSIGN;
@ -826,7 +826,7 @@ parameter SOA_REG = 1'b0;
parameter MULT_RESET_MODE = "SYNC";
endmodule
module MULT18X18 (...);
module MULT18X18(A, SIA, B, SIB, ASIGN, BSIGN, ASEL, BSEL, CE, CLK, RESET, DOUT, SOA, SOB);
input [17:0] A,SIA;
input [17:0] B,SIB;
input ASIGN,BSIGN;
@ -846,7 +846,7 @@ parameter SOA_REG = 1'b0;
parameter MULT_RESET_MODE = "SYNC";
endmodule
module MULT36X36 (...);
module MULT36X36(A, B, ASIGN, BSIGN, CE, CLK, RESET, DOUT);
input [35:0] A;
input [35:0] B;
input ASIGN,BSIGN;
@ -864,7 +864,7 @@ parameter BSIGN_REG = 1'b0;
parameter MULT_RESET_MODE = "SYNC";
endmodule
module MULTALU36X18 (...);
module MULTALU36X18(A, B, C, ASIGN, BSIGN, ACCLOAD, CE, CLK, RESET, CASI, DOUT, CASO);
input [17:0] A;
input [35:0] B;
input [53:0] C;
@ -889,7 +889,7 @@ parameter MULTALU36X18_MODE = 0;
parameter C_ADD_SUB = 1'b0;
endmodule
module MULTADDALU18X18 (...);
module MULTADDALU18X18(A0, B0, A1, B1, C, SIA, SIB, ASIGN, BSIGN, ASEL, BSEL, CASI, CE, CLK, RESET, ACCLOAD, DOUT, CASO, SOA, SOB);
input [17:0] A0;
input [17:0] B0;
input [17:0] A1;
@ -927,7 +927,7 @@ parameter MULTADDALU18X18_MODE = 0;
parameter MULT_RESET_MODE = "SYNC";
endmodule
module MULTALU18X18 (...);
module MULTALU18X18(A, B, CLK, CE, RESET, ASIGN, BSIGN, ACCLOAD, DSIGN, C, D, CASI, DOUT, CASO);
input [17:0] A, B;
input CLK,CE,RESET;
input ASIGN, BSIGN;
@ -953,7 +953,7 @@ parameter C_ADD_SUB = 1'b0;
parameter MULTALU18X18_MODE = 0;
endmodule
module ALU54D (...);
module ALU54D(A, B, ASIGN, BSIGN, ACCLOAD, CASI, CLK, CE, RESET, DOUT, CASO);
input [53:0] A, B;
input ASIGN,BSIGN;
input ACCLOAD;
@ -973,19 +973,19 @@ parameter ALUD_MODE = 0;
parameter ALU_RESET_MODE = "SYNC";
endmodule
module BUFG (...);
module BUFG(O, I);
output O;
input I;
endmodule
module BUFS (...);
module BUFS(O, I);
output O;
input I;
endmodule
module PLL (...);
module PLL(CLKIN, CLKFB, RESET, RESET_P, RESET_I, RESET_S, FBDSEL, IDSEL, ODSEL, PSDA, FDLY, DUTYDA, CLKOUT, LOCK, CLKOUTP, CLKOUTD, CLKOUTD3);
input CLKIN;
input CLKFB;
input RESET;
@ -1026,39 +1026,39 @@ parameter CLKOUTD3_SRC = "CLKOUT";
parameter DEVICE = "GW2A-18";
endmodule
module TLVDS_IBUF (...);
module TLVDS_IBUF(O, I, IB);
output O;
input I, IB;
endmodule
module TLVDS_TBUF (...);
module TLVDS_TBUF(O, OB, I, OEN);
output O, OB;
input I, OEN;
endmodule
module TLVDS_IOBUF (...);
module TLVDS_IOBUF(O, IO, IOB, I, OEN);
output O;
inout IO, IOB;
input I, OEN;
endmodule
module ELVDS_IBUF (...);
module ELVDS_IBUF(O, I, IB);
output O;
input I, IB;
endmodule
module ELVDS_TBUF (...);
module ELVDS_TBUF(O, OB, I, OEN);
output O, OB;
input I, OEN;
endmodule
module ELVDS_IOBUF (...);
module ELVDS_IOBUF(O, IO, IOB, I, OEN);
output O;
inout IO, IOB;
input I, OEN;
endmodule
module CLKDIV (...);
module CLKDIV(HCLKIN, RESETN, CALIB, CLKOUT);
input HCLKIN;
input RESETN;
input CALIB;
@ -1067,12 +1067,13 @@ parameter DIV_MODE = "2";
parameter GSREN = "false";
endmodule
module DHCEN (...);
module DHCEN(CLKIN, CE, CLKOUT);
input CLKIN,CE;
output CLKOUT;
endmodule
module DQS (...);
module DQS(DQSIN, PCLK, FCLK, RESET, READ, RCLKSEL, DLLSTEP, WSTEP, RLOADN, RMOVE, RDIR, WLOADN, WMOVE, WDIR, HOLD, DQSR90, DQSW0, DQSW270, RPOINT, WPOINT, RVALID
, RBURST, RFLAG, WFLAG);
input DQSIN,PCLK,FCLK,RESET;
input [3:0] READ;
input [2:0] RCLKSEL;
@ -1089,7 +1090,7 @@ output RVALID,RBURST, RFLAG, WFLAG;
parameter GSREN = "false";
endmodule
module DLLDLY (...);
module DLLDLY(CLKIN, DLLSTEP, DIR, LOADN, MOVE, CLKOUT, FLAG);
input CLKIN;
input [7:0] DLLSTEP;
input DIR,LOADN,MOVE;
@ -1100,67 +1101,67 @@ parameter DLY_SIGN = 1'b0;
parameter DLY_ADJ = 0;
endmodule
module DCS (...);
module DCS(CLK0, CLK1, CLK2, CLK3, SELFORCE, CLKSEL, CLKOUT);
input CLK0, CLK1, CLK2, CLK3, SELFORCE;
input [3:0] CLKSEL;
output CLKOUT;
parameter DCS_MODE = "RISING";
endmodule
module DQCE (...);
module DQCE(CLKIN, CE, CLKOUT);
input CLKIN;
input CE;
output CLKOUT;
endmodule
module CLKDIV2 (...);
module CLKDIV2(HCLKIN, RESETN, CLKOUT);
parameter GSREN = "false";
input HCLKIN, RESETN;
output CLKOUT;
endmodule
module IBUF_R (...);
module IBUF_R(I, RTEN, O);
input I;
input RTEN;
output O;
endmodule
module IOBUF_R (...);
module IOBUF_R(I, OEN, RTEN, O, IO);
input I,OEN;
input RTEN;
output O;
inout IO;
endmodule
module ELVDS_IBUF_R (...);
module ELVDS_IBUF_R(O, I, IB, RTEN);
output O;
input I, IB;
input RTEN;
endmodule
module ELVDS_IOBUF_R (...);
module ELVDS_IOBUF_R(O, IO, IOB, I, OEN, RTEN);
output O;
inout IO, IOB;
input I, OEN;
input RTEN;
endmodule
module OTP (...);
module OTP(CSB, SCLK, DOUT);
input CSB, SCLK;
output DOUT;
endmodule
module SAMB (...);
module SAMB(SPIAD, LOADN_SPIAD);
input [23:0] SPIAD;
input LOADN_SPIAD;
endmodule
module ELVDS_IBUF_MIPI (...);
module ELVDS_IBUF_MIPI(OH, OL, I, IB);
output OH, OL;
input I, IB;
endmodule
module MIPI_IBUF (...);
module MIPI_IBUF(OH, OL, OB, IO, IOB, I, IB, OEN, OENB, HSREN);
output OH, OL, OB;
inout IO, IOB;
input I, IB;
@ -1168,7 +1169,7 @@ input OEN, OENB;
input HSREN;
endmodule
module I3C_IOBUF (...);
module I3C_IOBUF(O, IO, I, MODESEL);
output O;
inout IO;
input I, MODESEL;

181
techlibs/gowin/cells_xtra_gw5a.v
View file

@ -1,75 +1,75 @@
// Created by cells_xtra.py
module LUT5 (...);
module LUT5(I0, I1, I2, I3, I4, F);
parameter INIT = 32'h00000000;
input I0, I1, I2, I3, I4;
output F;
endmodule
module LUT6 (...);
module LUT6(I0, I1, I2, I3, I4, I5, F);
parameter INIT = 64'h0000_0000_0000_0000;
input I0, I1, I2, I3, I4, I5;
output F;
endmodule
module LUT7 (...);
module LUT7(I0, I1, I2, I3, I4, I5, I6, F);
parameter INIT = 128'h0000_0000_0000_0000_0000_0000_0000_0000;
input I0, I1, I2, I3, I4, I5, I6;
output F;
endmodule
module LUT8 (...);
module LUT8(I0, I1, I2, I3, I4, I5, I6, I7, F);
parameter INIT = 256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000;
input I0, I1, I2, I3, I4, I5, I6, I7;
output F;
endmodule
module ROM16 (...);
module ROM16(AD, DO);
parameter INIT_0 = 16'h0000;
input [3:0] AD;
output DO;
endmodule
module INV (...);
module INV(I, O);
input I;
output O;
endmodule
module TLVDS_IBUF (...);
module TLVDS_IBUF(O, I, IB);
output O;
input I, IB;
endmodule
module TLVDS_TBUF (...);
module TLVDS_TBUF(O, OB, I, OEN);
output O, OB;
input I, OEN;
endmodule
module TLVDS_IOBUF (...);
module TLVDS_IOBUF(O, IO, IOB, I, OEN);
output O;
inout IO, IOB;
input I, OEN;
endmodule
module ELVDS_TBUF (...);
module ELVDS_TBUF(O, OB, I, OEN);
output O, OB;
input I, OEN;
endmodule
module ELVDS_IOBUF (...);
module ELVDS_IOBUF(O, IO, IOB, I, OEN);
output O;
inout IO, IOB;
input I, OEN;
endmodule
module MIPI_IBUF (...);
module MIPI_IBUF(OH, OL, OB, IO, IOB, I, IB, OEN, OENB, HSEN, HSREN);
output OH, OL, OB;
inout IO, IOB;
input I, IB;
@ -77,32 +77,33 @@ input OEN, OENB;
input HSEN, HSREN;
endmodule
module MIPI_OBUF_A (...);
module MIPI_OBUF_A(O, OB, I, IB, IL, MODESEL, IO, IOB, OEN, OENB);
output O, OB;
input I, IB, IL, MODESEL;
inout IO, IOB;
input OEN, OENB;
endmodule
module ELVDS_IOBUF_R (...);
module ELVDS_IOBUF_R(O, IO, IOB, I, OEN, RTEN);
output O;
inout IO, IOB;
input I, OEN;
input RTEN;
endmodule
module I3C_IOBUF (...);
module I3C_IOBUF(O, IO, I, MODESEL);
output O;
inout IO;
input I, MODESEL;
endmodule
module TLVDS_IBUF_ADC (...);
module TLVDS_IBUF_ADC(I, IB, ADCEN);
input I, IB;
input ADCEN;
endmodule
module MIPI_CPHY_IBUF (...);
module MIPI_CPHY_IBUF(OH0, OL0, OB0, OH1, OL1, OB1, OH2, OL2, OB2, IO0, IOB0, IO1, IOB1, IO2, IOB2, I0, IB0, I1, IB1, I2, IB2
, OEN, OENB, HSEN);
output OH0, OL0, OB0, OH1, OL1, OB1, OH2, OL2, OB2;
inout IO0, IOB0, IO1, IOB1, IO2, IOB2;
input I0, IB0, I1, IB1, I2, IB2;
@ -110,14 +111,15 @@ input OEN, OENB;
input HSEN;
endmodule
module MIPI_CPHY_OBUF (...);
module MIPI_CPHY_OBUF(O0, OB0, O1, OB1, O2, OB2, I0, IB0, IL0, I1, IB1, IL1, I2, IB2, IL2, IO0, IOB0, IO1, IOB1, IO2, IOB2
, OEN, OENB, MODESEL, VCOME);
output O0, OB0, O1, OB1, O2, OB2;
input I0, IB0, IL0, I1, IB1, IL1, I2, IB2, IL2;
inout IO0, IOB0, IO1, IOB1, IO2, IOB2;
input OEN, OENB, MODESEL, VCOME;
endmodule
module SDPB (...);
module SDPB(CLKA, CEA, CLKB, CEB, OCE, RESET, ADA, ADB, DI, BLKSELA, BLKSELB, DO);
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH_0 = 32;
parameter BIT_WIDTH_1 = 32;
@ -198,7 +200,7 @@ output [31:0] DO;
endmodule
module SDPX9B (...);
module SDPX9B(CLKA, CEA, CLKB, CEB, OCE, RESET, ADA, ADB, BLKSELA, BLKSELB, DI, DO);
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH_0 = 36;
parameter BIT_WIDTH_1 = 36;
@ -279,7 +281,7 @@ output [35:0] DO;
endmodule
module DPB (...);
module DPB(CLKA, CEA, CLKB, CEB, OCEA, OCEB, RESETA, RESETB, WREA, WREB, ADA, ADB, BLKSELA, BLKSELB, DIA, DIB, DOA, DOB);
parameter READ_MODE0 = 1'b0;
parameter READ_MODE1 = 1'b0;
parameter WRITE_MODE0 = 2'b00;
@ -364,7 +366,7 @@ output [15:0] DOA, DOB;
endmodule
module DPX9B (...);
module DPX9B(CLKA, CEA, CLKB, CEB, OCEA, OCEB, RESETA, RESETB, WREA, WREB, ADA, ADB, DIA, DIB, BLKSELA, BLKSELB, DOA, DOB);
parameter READ_MODE0 = 1'b0;
parameter READ_MODE1 = 1'b0;
parameter WRITE_MODE0 = 2'b00;
@ -449,7 +451,7 @@ output [17:0] DOA, DOB;
endmodule
module pROM (...);
module pROM(CLK, CE, OCE, RESET, AD, DO);
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH = 32;
parameter RESET_MODE = "SYNC";
@ -525,7 +527,7 @@ output [31:0] DO;
endmodule
module pROMX9 (...);
module pROMX9(CLK, CE, OCE, RESET, AD, DO);
parameter READ_MODE = 1'b0;
parameter BIT_WIDTH = 36;
parameter RESET_MODE = "SYNC";
@ -601,7 +603,7 @@ output [35:0] DO;
endmodule
module SDP36KE (...);
module SDP36KE(CLKA, CEA, CLKB, CEB, OCE, RESET, ADA, ADB, DI, DIP, BLKSELA, BLKSELB, DECCI, SECCI, DO, DOP, DECCO, SECCO, ECCP);
parameter ECC_WRITE_EN="TRUE";
parameter ECC_READ_EN="TRUE";
parameter READ_MODE = 1'b0;
@ -768,7 +770,7 @@ output [7:0] ECCP;
endmodule
module SDP136K (...);
module SDP136K(CLKA, CLKB, WE, RE, ADA, ADB, DI, DO);
input CLKA, CLKB;
input WE, RE;
input [10:0] ADA, ADB;
@ -776,7 +778,7 @@ input [67:0] DI;
output [67:0] DO;
endmodule
module MULTADDALU12X12 (...);
module MULTADDALU12X12(DOUT, CASO, A0, B0, A1, B1, CASI, ACCSEL, CASISEL, ADDSUB, CLK, CE, RESET);
parameter A0REG_CLK = "BYPASS";
parameter A0REG_CE = "CE0";
parameter A0REG_RESET = "RESET0";
@ -842,7 +844,7 @@ input [1:0] ADDSUB;
input [1:0] CLK, CE, RESET;
endmodule
module MULTALU27X18 (...);
module MULTALU27X18(DOUT, CASO, SOA, A, SIA, B, C, D, CASI, ACCSEL, PSEL, ASEL, PADDSUB, CSEL, CASISEL, ADDSUB, CLK, CE, RESET);
parameter AREG_CLK = "BYPASS";
parameter AREG_CE = "CE0";
parameter AREG_RESET = "RESET0";
@ -937,7 +939,7 @@ input [1:0] ADDSUB;
input [1:0] CLK, CE, RESET;
endmodule
module MULT12X12 (...);
module MULT12X12(DOUT, A, B, CLK, CE, RESET);
parameter AREG_CLK = "BYPASS";
parameter AREG_CE = "CE0";
parameter AREG_RESET = "RESET0";
@ -956,7 +958,7 @@ input [11:0] A, B;
input [1:0] CLK, CE, RESET;
endmodule
module MULT27X36 (...);
module MULT27X36(DOUT, A, B, D, CLK, CE, RESET, PSEL, PADDSUB);
parameter AREG_CLK = "BYPASS";
parameter AREG_CE = "CE0";
parameter AREG_RESET = "RESET0";
@ -992,7 +994,7 @@ input PSEL;
input PADDSUB;
endmodule
module MULTACC (...);
module MULTACC(DATAO, CASO, CE, CLK, COFFIN0, COFFIN1, COFFIN2, DATAIN0, DATAIN1, DATAIN2, RSTN, CASI);
output [23:0] DATAO, CASO;
input CE, CLK;
input [5:0] COFFIN0, COFFIN1, COFFIN2;
@ -1010,7 +1012,7 @@ parameter CASI_EN = "FALSE";
parameter CASO_EN = "FALSE";
endmodule
module IDDR_MEM (...);
module IDDR_MEM(D, ICLK, PCLK, WADDR, RADDR, RESET, Q0, Q1);
input D, ICLK, PCLK;
input [2:0] WADDR;
input [2:0] RADDR;
@ -1019,7 +1021,7 @@ output Q0,Q1;
endmodule
module ODDR_MEM (...);
module ODDR_MEM(D0, D1, TX, PCLK, TCLK, RESET, Q0, Q1);
parameter TCLK_SOURCE = "DQSW";
parameter TXCLK_POL = 1'b0;
input D0, D1;
@ -1028,7 +1030,7 @@ output Q0, Q1;
endmodule
module IDES4_MEM (...);
module IDES4_MEM(PCLK, D, ICLK, FCLK, RESET, CALIB, WADDR, RADDR, Q0, Q1, Q2, Q3);
input PCLK, D, ICLK, FCLK, RESET, CALIB;
input [2:0] WADDR;
input [2:0] RADDR;
@ -1036,7 +1038,7 @@ output Q0,Q1,Q2,Q3;
endmodule
module IDES8_MEM (...);
module IDES8_MEM(PCLK, D, ICLK, FCLK, RESET, CALIB, WADDR, RADDR, Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7);
input PCLK, D, ICLK, FCLK, RESET, CALIB;
input [2:0] WADDR;
input [2:0] RADDR;
@ -1044,19 +1046,20 @@ output Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7;
endmodule
module IDES14 (...);
module IDES14(D, FCLK, PCLK, CALIB, RESET, Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13);
input D, FCLK, PCLK, CALIB,RESET;
output Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13;
endmodule
module IDES32 (...);
module IDES32(D, FCLK, PCLK, CALIB, RESET, Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15
, Q16, Q17, Q18, Q19, Q20, Q21, Q22, Q23, Q24, Q25, Q26, Q27, Q28, Q29, Q30, Q31);
input D, FCLK, PCLK, CALIB,RESET;
output Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15, Q16, Q17, Q18, Q19, Q20, Q21, Q22, Q23, Q24, Q25, Q26, Q27, Q28, Q29, Q30, Q31;
endmodule
module OSER4_MEM (...);
module OSER4_MEM(D0, D1, D2, D3, TX0, TX1, PCLK, FCLK, TCLK, RESET, Q0, Q1);
parameter HWL = "false";
parameter TCLK_SOURCE = "DQSW";
parameter TXCLK_POL = 1'b0;
@ -1067,7 +1070,7 @@ output Q0, Q1;
endmodule
module OSER8_MEM (...);
module OSER8_MEM(D0, D1, D2, D3, D4, D5, D6, D7, TX0, TX1, TX2, TX3, PCLK, FCLK, TCLK, RESET, Q0, Q1);
parameter HWL = "false";
parameter TCLK_SOURCE = "DQSW";
parameter TXCLK_POL = 1'b0;
@ -1078,13 +1081,13 @@ output Q0, Q1;
endmodule
module OSER14 (...);
module OSER14(D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, PCLK, FCLK, RESET, Q);
input D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13;
input PCLK, FCLK, RESET;
output Q;
endmodule
module IODELAY (...);
module IODELAY(DI, SDTAP, VALUE, DLYSTEP, DF, DO);
parameter C_STATIC_DLY = 0;
parameter DYN_DLY_EN = "FALSE";
parameter ADAPT_EN = "FALSE";
@ -1097,7 +1100,7 @@ output DO;
endmodule
module OSIDES32 (...);
module OSIDES32(Q, D, PCLK, FCLKP, FCLKN, FCLKQP, FCLKQN, RESET, DF0, DF1, SDTAP0, SDTAP1, VALUE0, VALUE1, DLYSTEP0, DLYSTEP1);
output [31:0] Q;
input D;
input PCLK, FCLKP, FCLKN, FCLKQP, FCLKQN;
@ -1114,7 +1117,8 @@ parameter DYN_DLY_EN_1 = "FALSE";
parameter ADAPT_EN_1 = "FALSE";
endmodule
module OSIDES64 (...);
module OSIDES64(Q, D, PCLK, FCLKP, FCLKN, FCLKQP, FCLKQN, RESET, DF0, DF1, DF2, DF3, SDTAP0, SDTAP1, SDTAP2, SDTAP3, VALUE0, VALUE1, VALUE2, VALUE3, DLYSTEP0
, DLYSTEP1, DLYSTEP2, DLYSTEP3);
output [63:0] Q;
input D;
input PCLK, FCLKP, FCLKN, FCLKQP, FCLKQN;
@ -1137,20 +1141,20 @@ parameter DYN_DLY_EN_3 = "FALSE";
parameter ADAPT_EN_3 = "FALSE";
endmodule
module DCE (...);
module DCE(CLKIN, CE, CLKOUT);
input CLKIN;
input CE;
output CLKOUT;
endmodule
module DCS (...);
module DCS(CLKIN0, CLKIN1, CLKIN2, CLKIN3, SELFORCE, CLKSEL, CLKOUT);
input CLKIN0, CLKIN1, CLKIN2, CLKIN3, SELFORCE;
input [3:0] CLKSEL;
output CLKOUT;
parameter DCS_MODE = "RISING";
endmodule
module DDRDLL (...);
module DDRDLL(CLKIN, STOP, UPDNCNTL, RESET, STEP, LOCK);
input CLKIN;
input STOP;
input UPDNCNTL;
@ -1163,7 +1167,7 @@ parameter SCAL_EN = "TRUE";
parameter DIV_SEL = 1'b0;
endmodule
module DLLDLY (...);
module DLLDLY(CLKIN, DLLSTEP, CSTEP, LOADN, MOVE, CLKOUT, FLAG);
input CLKIN;
input [7:0] DLLSTEP, CSTEP;
input LOADN,MOVE;
@ -1176,7 +1180,7 @@ parameter ADAPT_EN = "FALSE";
parameter STEP_SEL = 1'b0;
endmodule
module CLKDIV (...);
module CLKDIV(HCLKIN, RESETN, CALIB, CLKOUT);
input HCLKIN;
input RESETN;
input CALIB;
@ -1184,24 +1188,24 @@ output CLKOUT;
parameter DIV_MODE = "2";
endmodule
module CLKDIV2 (...);
module CLKDIV2(HCLKIN, RESETN, CLKOUT);
input HCLKIN, RESETN;
output CLKOUT;
endmodule
module DHCE (...);
module DHCE(CLKIN, CEN, CLKOUT);
input CLKIN;
input CEN;
output CLKOUT;
endmodule
module OSCA (...);
module OSCA(OSCOUT, OSCEN);
parameter FREQ_DIV = 100;
output OSCOUT;
input OSCEN;
endmodule
module OSCB (...);
module OSCB(OSCOUT, OSCREF, OSCEN, FMODE, RTRIM, RTCTRIM);
parameter FREQ_MODE = "25";
parameter FREQ_DIV = 10;
parameter DYN_TRIM_EN = "FALSE";
@ -1212,7 +1216,9 @@ input [7:0] RTRIM;
input [5:0] RTCTRIM;
endmodule
module PLL (...);
module PLL(CLKIN, CLKFB, RESET, PLLPWD, RESET_I, RESET_O, FBDSEL, IDSEL, MDSEL, MDSEL_FRAC, ODSEL0, ODSEL0_FRAC, ODSEL1, ODSEL2, ODSEL3, ODSEL4, ODSEL5, ODSEL6, DT0, DT1, DT2
, DT3, ICPSEL, LPFRES, LPFCAP, PSSEL, PSDIR, PSPULSE, ENCLK0, ENCLK1, ENCLK2, ENCLK3, ENCLK4, ENCLK5, ENCLK6, SSCPOL, SSCON, SSCMDSEL, SSCMDSEL_FRAC, LOCK, CLKOUT0, CLKOUT1
, CLKOUT2, CLKOUT3, CLKOUT4, CLKOUT5, CLKOUT6, CLKFBOUT);
input CLKIN;
input CLKFB;
input RESET;
@ -1354,7 +1360,8 @@ parameter LPF_CAP = 2'b00;
parameter SSC_EN = "FALSE";
endmodule
module PLLA (...);
module PLLA(CLKIN, CLKFB, RESET, PLLPWD, RESET_I, RESET_O, PSSEL, PSDIR, PSPULSE, SSCPOL, SSCON, SSCMDSEL, SSCMDSEL_FRAC, MDCLK, MDOPC, MDAINC, MDWDI, MDRDO, LOCK, CLKOUT0, CLKOUT1
, CLKOUT2, CLKOUT3, CLKOUT4, CLKOUT5, CLKOUT6, CLKFBOUT);
input CLKIN;
input CLKFB;
input RESET;
@ -1462,7 +1469,14 @@ parameter LPF_CAP = 2'b00;
parameter SSC_EN = "FALSE";
endmodule
module AE350_SOC (...);
module AE350_SOC(POR_N, HW_RSTN, CORE_CLK, DDR_CLK, AHB_CLK, APB_CLK, DBG_TCK, RTC_CLK, CORE_CE, AXI_CE, DDR_CE, AHB_CE, APB_CE, APB2AHB_CE, SCAN_TEST, SCAN_EN, PRESETN, HRESETN, DDR_RSTN, GP_INT, DMA_REQ
, DMA_ACK, CORE0_WFI_MODE, WAKEUP_IN, RTC_WAKEUP, TEST_CLK, TEST_MODE, TEST_RSTN, ROM_HADDR, ROM_HRDATA, ROM_HREADY, ROM_HRESP, ROM_HTRANS, ROM_HWRITE, APB_PADDR, APB_PENABLE, APB_PRDATA, APB_PREADY, APB_PSEL, APB_PWDATA, APB_PWRITE, APB_PSLVERR
, APB_PPROT, APB_PSTRB, EXTS_HRDATA, EXTS_HREADYIN, EXTS_HRESP, EXTS_HADDR, EXTS_HBURST, EXTS_HPROT, EXTS_HSEL, EXTS_HSIZE, EXTS_HTRANS, EXTS_HWDATA, EXTS_HWRITE, EXTM_HADDR, EXTM_HBURST, EXTM_HPROT, EXTM_HRDATA, EXTM_HREADY, EXTM_HREADYOUT, EXTM_HRESP, EXTM_HSEL
, EXTM_HSIZE, EXTM_HTRANS, EXTM_HWDATA, EXTM_HWRITE, DDR_HADDR, DDR_HBURST, DDR_HPROT, DDR_HRDATA, DDR_HREADY, DDR_HRESP, DDR_HSIZE, DDR_HTRANS, DDR_HWDATA, DDR_HWRITE, TMS_IN, TRST_IN, TDI_IN, TDO_OUT, TDO_OE, SPI2_HOLDN_IN, SPI2_WPN_IN
, SPI2_CLK_IN, SPI2_CSN_IN, SPI2_MISO_IN, SPI2_MOSI_IN, SPI2_HOLDN_OUT, SPI2_HOLDN_OE, SPI2_WPN_OUT, SPI2_WPN_OE, SPI2_CLK_OUT, SPI2_CLK_OE, SPI2_CSN_OUT, SPI2_CSN_OE, SPI2_MISO_OUT, SPI2_MISO_OE, SPI2_MOSI_OUT, SPI2_MOSI_OE, I2C_SCL_IN, I2C_SDA_IN, I2C_SCL, I2C_SDA, UART1_TXD
, UART1_RTSN, UART1_RXD, UART1_CTSN, UART1_DSRN, UART1_DCDN, UART1_RIN, UART1_DTRN, UART1_OUT1N, UART1_OUT2N, UART2_TXD, UART2_RTSN, UART2_RXD, UART2_CTSN, UART2_DCDN, UART2_DSRN, UART2_RIN, UART2_DTRN, UART2_OUT1N, UART2_OUT2N, CH0_PWM, CH0_PWMOE
, CH1_PWM, CH1_PWMOE, CH2_PWM, CH2_PWMOE, CH3_PWM, CH3_PWMOE, GPIO_IN, GPIO_OE, GPIO_OUT, SCAN_IN, INTEG_TCK, INTEG_TDI, INTEG_TMS, INTEG_TRST, INTEG_TDO, SCAN_OUT, PGEN_CHAIN_I, PRDYN_CHAIN_O, EMA, EMAW, EMAS
, RET1N, RET2N);
input POR_N;
input HW_RSTN;
input CORE_CLK;
@ -1614,7 +1628,8 @@ input RET1N;
input RET2N;
endmodule
module AE350_RAM (...);
module AE350_RAM(POR_N, HW_RSTN, CORE_CLK, AHB_CLK, APB_CLK, RTC_CLK, CORE_CE, AXI_CE, AHB_CE, EXTM_HADDR, EXTM_HBURST, EXTM_HPROT, EXTM_HRDATA, EXTM_HREADY, EXTM_HREADYOUT, EXTM_HRESP, EXTM_HSEL, EXTM_HSIZE, EXTM_HTRANS, EXTM_HWDATA, EXTM_HWRITE
, EMA, EMAW, EMAS, RET1N, RET2N);
input POR_N;
input HW_RSTN;
input CORE_CLK;
@ -1643,20 +1658,20 @@ input RET1N;
input RET2N;
endmodule
module SAMB (...);
module SAMB(SPIAD, LOAD, ADWSEL);
parameter MODE = 2'b00;
input [23:0] SPIAD;
input LOAD;
input ADWSEL;
endmodule
module OTP (...);
module OTP(CLK, READ, SHIFT, DOUT);
parameter MODE = 2'b01;
input CLK, READ, SHIFT;
output DOUT;
endmodule
module CMSER (...);
module CMSER(RUNNING, CRCERR, CRCDONE, ECCCORR, ECCUNCORR, ERRLOC, ECCDEC, DSRRD, DSRWR, ASRRESET, ASRINC, REFCLK, CLK, SEREN, ERRINJECT, ERRINJLOC);
output RUNNING;
output CRCERR;
output CRCDONE;
@ -1675,7 +1690,7 @@ input ERRINJECT;
input [6:0] ERRINJLOC;
endmodule
module CMSERA (...);
module CMSERA(RUNNING, CRCERR, CRCDONE, ECCCORR, ECCUNCORR, ERR0LOC, ERR1LOC, ECCDEC, DSRRD, DSRWR, ASRRESET, ASRINC, REFCLK, CLK, SEREN, ERR0INJECT, ERR1INJECT, ERRINJ0LOC, ERRINJ1LOC);
output RUNNING;
output CRCERR;
output CRCDONE;
@ -1695,7 +1710,7 @@ input ERR0INJECT,ERR1INJECT;
input [6:0] ERRINJ0LOC,ERRINJ1LOC;
endmodule
module CMSERB (...);
module CMSERB(RUNNING, CRCERR, CRCDONE, ECCCORR, ECCUNCORR, ERRLOC, ECCDEC, DSRRD, DSRWR, ASRRESET, ASRINC, REFCLK, CLK, SEREN, ERR0INJECT, ERR1INJECT, ERRINJ0LOC, ERRINJ1LOC);
output RUNNING;
output CRCERR;
output CRCDONE;
@ -1714,13 +1729,13 @@ input ERR0INJECT,ERR1INJECT;
input [6:0] ERRINJ0LOC,ERRINJ1LOC;
endmodule
module SAMBA (...);
module SAMBA(SPIAD, LOAD);
parameter MODE = 2'b00;
input SPIAD;
input LOAD;
endmodule
module LICD (...);
module LICD();
parameter STAGE_NUM = 2'b00;
parameter ENCDEC_NUM = 2'b00;
parameter CODE_WIDTH = 2'b00;
@ -1728,7 +1743,13 @@ module LICD (...);
parameter INTERLEAVE_MODE = 3'b000;
endmodule
module MIPI_DPHY (...);
module MIPI_DPHY(RX_CLK_O, TX_CLK_O, D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD, D3LN_HSRXD, D0LN_HSRXD_VLD, D1LN_HSRXD_VLD, D2LN_HSRXD_VLD, D3LN_HSRXD_VLD, D0LN_HSRX_DREN, D1LN_HSRX_DREN, D2LN_HSRX_DREN, D3LN_HSRX_DREN, DI_LPRX0_N, DI_LPRX0_P, DI_LPRX1_N, DI_LPRX1_P, DI_LPRX2_N, DI_LPRX2_P, DI_LPRX3_N
, DI_LPRX3_P, DI_LPRXCK_N, DI_LPRXCK_P, CK_N, CK_P, D0_N, D0_P, D1_N, D1_P, D2_N, D2_P, D3_N, D3_P, HSRX_STOP, HSTXEN_LN0, HSTXEN_LN1, HSTXEN_LN2, HSTXEN_LN3, HSTXEN_LNCK, LPTXEN_LN0, LPTXEN_LN1
, LPTXEN_LN2, LPTXEN_LN3, LPTXEN_LNCK, PWRON_RX, PWRON_TX, RESET, RX_CLK_1X, TX_CLK_1X, TXDPEN_LN0, TXDPEN_LN1, TXDPEN_LN2, TXDPEN_LN3, TXDPEN_LNCK, TXHCLK_EN, CKLN_HSTXD, D0LN_HSTXD, D1LN_HSTXD, D2LN_HSTXD, D3LN_HSTXD, HSTXD_VLD, CK0
, CK90, CK180, CK270, DO_LPTX0_N, DO_LPTX1_N, DO_LPTX2_N, DO_LPTX3_N, DO_LPTXCK_N, DO_LPTX0_P, DO_LPTX1_P, DO_LPTX2_P, DO_LPTX3_P, DO_LPTXCK_P, HSRX_EN_CK, HSRX_EN_D0, HSRX_EN_D1, HSRX_EN_D2, HSRX_EN_D3, HSRX_ODTEN_CK, HSRX_ODTEN_D0, HSRX_ODTEN_D1
, HSRX_ODTEN_D2, HSRX_ODTEN_D3, LPRX_EN_CK, LPRX_EN_D0, LPRX_EN_D1, LPRX_EN_D2, LPRX_EN_D3, RX_DRST_N, TX_DRST_N, WALIGN_DVLD, MRDATA, MA_INC, MCLK, MOPCODE, MWDATA, ALPEDO_LANE0, ALPEDO_LANE1, ALPEDO_LANE2, ALPEDO_LANE3, ALPEDO_LANECK, D1LN_DESKEW_DONE
, D2LN_DESKEW_DONE, D3LN_DESKEW_DONE, D0LN_DESKEW_DONE, D1LN_DESKEW_ERROR, D2LN_DESKEW_ERROR, D3LN_DESKEW_ERROR, D0LN_DESKEW_ERROR, D0LN_DESKEW_REQ, D1LN_DESKEW_REQ, D2LN_DESKEW_REQ, D3LN_DESKEW_REQ, HSRX_DLYDIR_LANE0, HSRX_DLYDIR_LANE1, HSRX_DLYDIR_LANE2, HSRX_DLYDIR_LANE3, HSRX_DLYDIR_LANECK, HSRX_DLYLDN_LANE0, HSRX_DLYLDN_LANE1, HSRX_DLYLDN_LANE2, HSRX_DLYLDN_LANE3, HSRX_DLYLDN_LANECK
, HSRX_DLYMV_LANE0, HSRX_DLYMV_LANE1, HSRX_DLYMV_LANE2, HSRX_DLYMV_LANE3, HSRX_DLYMV_LANECK, ALP_EDEN_LANE0, ALP_EDEN_LANE1, ALP_EDEN_LANE2, ALP_EDEN_LANE3, ALP_EDEN_LANECK, ALPEN_LN0, ALPEN_LN1, ALPEN_LN2, ALPEN_LN3, ALPEN_LNCK);
output RX_CLK_O, TX_CLK_O;
output [15:0] D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD, D3LN_HSRXD;
output D0LN_HSRXD_VLD,D1LN_HSRXD_VLD,D2LN_HSRXD_VLD,D3LN_HSRXD_VLD;
@ -2024,7 +2045,13 @@ parameter TEST_P_IMP_LN3 = 1'b0 ;
parameter TEST_P_IMP_LNCK = 1'b0 ;
endmodule
module MIPI_DPHYA (...);
module MIPI_DPHYA(RX_CLK_O, TX_CLK_O, D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD, D3LN_HSRXD, D0LN_HSRXD_VLD, D1LN_HSRXD_VLD, D2LN_HSRXD_VLD, D3LN_HSRXD_VLD, D0LN_HSRX_DREN, D1LN_HSRX_DREN, D2LN_HSRX_DREN, D3LN_HSRX_DREN, DI_LPRX0_N, DI_LPRX0_P, DI_LPRX1_N, DI_LPRX1_P, DI_LPRX2_N, DI_LPRX2_P, DI_LPRX3_N
, DI_LPRX3_P, DI_LPRXCK_N, DI_LPRXCK_P, CK_N, CK_P, D0_N, D0_P, D1_N, D1_P, D2_N, D2_P, D3_N, D3_P, HSRX_STOP, HSTXEN_LN0, HSTXEN_LN1, HSTXEN_LN2, HSTXEN_LN3, HSTXEN_LNCK, LPTXEN_LN0, LPTXEN_LN1
, LPTXEN_LN2, LPTXEN_LN3, LPTXEN_LNCK, PWRON_RX, PWRON_TX, RESET, RX_CLK_1X, TX_CLK_1X, TXDPEN_LN0, TXDPEN_LN1, TXDPEN_LN2, TXDPEN_LN3, TXDPEN_LNCK, TXHCLK_EN, CKLN_HSTXD, D0LN_HSTXD, D1LN_HSTXD, D2LN_HSTXD, D3LN_HSTXD, HSTXD_VLD, CK0
, CK90, CK180, CK270, DO_LPTX0_N, DO_LPTX1_N, DO_LPTX2_N, DO_LPTX3_N, DO_LPTXCK_N, DO_LPTX0_P, DO_LPTX1_P, DO_LPTX2_P, DO_LPTX3_P, DO_LPTXCK_P, HSRX_EN_CK, HSRX_EN_D0, HSRX_EN_D1, HSRX_EN_D2, HSRX_EN_D3, HSRX_ODTEN_CK, HSRX_ODTEN_D0, HSRX_ODTEN_D1
, HSRX_ODTEN_D2, HSRX_ODTEN_D3, LPRX_EN_CK, LPRX_EN_D0, LPRX_EN_D1, LPRX_EN_D2, LPRX_EN_D3, RX_DRST_N, TX_DRST_N, WALIGN_DVLD, MRDATA, MA_INC, MCLK, MOPCODE, MWDATA, SPLL_CKN, SPLL_CKP, ALPEDO_LANE0, ALPEDO_LANE1, ALPEDO_LANE2, ALPEDO_LANE3
, ALPEDO_LANECK, D1LN_DESKEW_DONE, D2LN_DESKEW_DONE, D3LN_DESKEW_DONE, D0LN_DESKEW_DONE, D1LN_DESKEW_ERROR, D2LN_DESKEW_ERROR, D3LN_DESKEW_ERROR, D0LN_DESKEW_ERROR, D0LN_DESKEW_REQ, D1LN_DESKEW_REQ, D2LN_DESKEW_REQ, D3LN_DESKEW_REQ, HSRX_DLYDIR_LANE0, HSRX_DLYDIR_LANE1, HSRX_DLYDIR_LANE2, HSRX_DLYDIR_LANE3, HSRX_DLYDIR_LANECK, HSRX_DLYLDN_LANE0, HSRX_DLYLDN_LANE1, HSRX_DLYLDN_LANE2
, HSRX_DLYLDN_LANE3, HSRX_DLYLDN_LANECK, HSRX_DLYMV_LANE0, HSRX_DLYMV_LANE1, HSRX_DLYMV_LANE2, HSRX_DLYMV_LANE3, HSRX_DLYMV_LANECK, ALP_EDEN_LANE0, ALP_EDEN_LANE1, ALP_EDEN_LANE2, ALP_EDEN_LANE3, ALP_EDEN_LANECK, ALPEN_LN0, ALPEN_LN1, ALPEN_LN2, ALPEN_LN3, ALPEN_LNCK);
output RX_CLK_O, TX_CLK_O;
output [15:0] D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD, D3LN_HSRXD;
output D0LN_HSRXD_VLD,D1LN_HSRXD_VLD,D2LN_HSRXD_VLD,D3LN_HSRXD_VLD;
@ -2323,7 +2350,12 @@ parameter TEST_P_IMP_LN3 = 1'b0 ;
parameter TEST_P_IMP_LNCK = 1'b0 ;
endmodule
module MIPI_CPHY (...);
module MIPI_CPHY(D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD, D0LN_HSRXD_VLD, D1LN_HSRXD_VLD, D2LN_HSRXD_VLD, D0LN_HSRX_DEMAP_INVLD, D1LN_HSRX_DEMAP_INVLD, D2LN_HSRX_DEMAP_INVLD, D0LN_HSRX_FIFO_RDE_ERR, D0LN_HSRX_FIFO_WRF_ERR, D1LN_HSRX_FIFO_RDE_ERR, D1LN_HSRX_FIFO_WRF_ERR, D2LN_HSRX_FIFO_RDE_ERR, D2LN_HSRX_FIFO_WRF_ERR, D0LN_HSRX_WA, D1LN_HSRX_WA, D2LN_HSRX_WA, D0LN_RX_CLK_1X_O, D1LN_RX_CLK_1X_O, D2LN_RX_CLK_1X_O
, HSTX_FIFO_AE, HSTX_FIFO_AF, HSTX_FIFO_RDE_ERR, HSTX_FIFO_WRF_ERR, RX_CLK_MUXED, TX_CLK_1X_O, DI_LPRX0_A, DI_LPRX0_B, DI_LPRX0_C, DI_LPRX1_A, DI_LPRX1_B, DI_LPRX1_C, DI_LPRX2_A, DI_LPRX2_B, DI_LPRX2_C, MDRP_RDATA, D0A, D0B, D0C, D1A, D1B
, D1C, D2A, D2B, D2C, D0LN_HSRX_EN, D0LN_HSTX_EN, D1LN_HSRX_EN, D1LN_HSTX_EN, D2LN_HSRX_EN, D2LN_HSTX_EN, D0LN_HSTX_DATA, D1LN_HSTX_DATA, D2LN_HSTX_DATA, D0LN_HSTX_DATA_VLD, D1LN_HSTX_DATA_VLD, D2LN_HSTX_DATA_VLD, D0LN_HSTX_MAP_DIS, D1LN_HSTX_MAP_DIS, D2LN_HSTX_MAP_DIS, D0LN_RX_CLK_1X_I, D1LN_RX_CLK_1X_I
, D2LN_RX_CLK_1X_I, D0LN_RX_DRST_N, D0LN_TX_DRST_N, D1LN_RX_DRST_N, D1LN_TX_DRST_N, D2LN_RX_DRST_N, D2LN_TX_DRST_N, HSTX_ENLN0, HSTX_ENLN1, HSTX_ENLN2, LPTX_ENLN0, LPTX_ENLN1, LPTX_ENLN2, MDRP_A_D_I, MDRP_A_INC_I, MDRP_CLK_I, MDRP_OPCODE_I, PWRON_RX_LN0, PWRON_RX_LN1, PWRON_RX_LN2, PWRON_TX
, ARST_RXLN0, ARST_RXLN1, ARST_RXLN2, ARSTN_TX, RX_CLK_EN_LN0, RX_CLK_EN_LN1, RX_CLK_EN_LN2, TX_CLK_1X_I, TXDP_ENLN0, TXDP_ENLN1, TXDP_ENLN2, TXHCLK_EN, DO_LPTX_A_LN0, DO_LPTX_A_LN1, DO_LPTX_A_LN2, DO_LPTX_B_LN0, DO_LPTX_B_LN1, DO_LPTX_B_LN2, DO_LPTX_C_LN0, DO_LPTX_C_LN1, DO_LPTX_C_LN2
, GPLL_CK0, GPLL_CK90, GPLL_CK180, GPLL_CK270, HSRX_EN_D0, HSRX_EN_D1, HSRX_EN_D2, HSRX_ODT_EN_D0, HSRX_ODT_EN_D1, HSRX_ODT_EN_D2, LPRX_EN_D0, LPRX_EN_D1, LPRX_EN_D2, SPLL0_CKN, SPLL0_CKP, SPLL1_CKN, SPLL1_CKP);
output [41:0] D0LN_HSRXD, D1LN_HSRXD, D2LN_HSRXD;
output D0LN_HSRXD_VLD, D1LN_HSRXD_VLD, D2LN_HSRXD_VLD;
output [1:0] D0LN_HSRX_DEMAP_INVLD, D1LN_HSRX_DEMAP_INVLD, D2LN_HSRX_DEMAP_INVLD;
@ -2455,29 +2487,30 @@ parameter EQ_PBIAS_LN2 = 4'b0100;
parameter EQ_ZLD_LN2 = 4'b1000;
endmodule
module GTR12_QUAD (...);
module GTR12_QUAD();
parameter POSITION = "Q0";
endmodule
module GTR12_UPAR (...);
module GTR12_UPAR();
endmodule
module GTR12_PMAC (...);
module GTR12_PMAC();
endmodule
module GTR12_QUADA (...);
module GTR12_QUADA();
endmodule
module GTR12_UPARA (...);
module GTR12_UPARA();
endmodule
module GTR12_PMACA (...);
module GTR12_PMACA();
endmodule
module GTR12_QUADB (...);
module GTR12_QUADB();
endmodule
module DQS (...);
module DQS(DQSIN, PCLK, FCLK, RESET, READ, RCLKSEL, DLLSTEP, WSTEP, RLOADN, RMOVE, RDIR, WLOADN, WMOVE, WDIR, HOLD, DQSR90, DQSW0, DQSW270, RPOINT, WPOINT, RVALID
, RBURST, RFLAG, WFLAG);
input DQSIN,PCLK,FCLK,RESET;
input [3:0] READ;
input [2:0] RCLKSEL;

124
techlibs/lattice/cells_bb_ecp5.v
View file

@ -1,24 +1,29 @@
// Created by cells_xtra.py from Lattice models
(* blackbox *) (* keep *)
module GSR (...);
module GSR(GSR);
input GSR;
endmodule
(* blackbox *)
module PUR (...);
module PUR(PUR);
parameter RST_PULSE = 1;
input PUR;
endmodule
(* blackbox *) (* keep *)
module SGSR (...);
module SGSR(GSR, CLK);
input GSR;
input CLK;
endmodule
(* blackbox *)
module PDPW16KD (...);
module PDPW16KD(DI35, DI34, DI33, DI32, DI31, DI30, DI29, DI28, DI27, DI26, DI25, DI24, DI23, DI22, DI21, DI20, DI19, DI18, DI17, DI16, DI15
, DI14, DI13, DI12, DI11, DI10, DI9, DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0, ADW8, ADW7, ADW6, ADW5, ADW4, ADW3
, ADW2, ADW1, ADW0, BE3, BE2, BE1, BE0, CEW, CLKW, CSW2, CSW1, CSW0, ADR13, ADR12, ADR11, ADR10, ADR9, ADR8, ADR7, ADR6, ADR5
, ADR4, ADR3, ADR2, ADR1, ADR0, CER, OCER, CLKR, CSR2, CSR1, CSR0, RST, DO35, DO34, DO33, DO32, DO31, DO30, DO29, DO28, DO27
, DO26, DO25, DO24, DO23, DO22, DO21, DO20, DO19, DO18, DO17, DO16, DO15, DO14, DO13, DO12, DO11, DO10, DO9, DO8, DO7, DO6
, DO5, DO4, DO3, DO2, DO1, DO0);
parameter CLKRMUX = "CLKR";
parameter CLKWMUX = "CLKW";
parameter DATA_WIDTH_W = 36;
@ -208,7 +213,18 @@ module PDPW16KD (...);
endmodule
(* blackbox *)
module MULT18X18D (...);
module MULT18X18D(A17, A16, A15, A14, A13, A12, A11, A10, A9, A8, A7, A6, A5, A4, A3, A2, A1, A0, B17, B16, B15
, B14, B13, B12, B11, B10, B9, B8, B7, B6, B5, B4, B3, B2, B1, B0, C17, C16, C15, C14, C13, C12
, C11, C10, C9, C8, C7, C6, C5, C4, C3, C2, C1, C0, SIGNEDA, SIGNEDB, SOURCEA, SOURCEB, CLK3, CLK2, CLK1, CLK0, CE3
, CE2, CE1, CE0, RST3, RST2, RST1, RST0, SRIA17, SRIA16, SRIA15, SRIA14, SRIA13, SRIA12, SRIA11, SRIA10, SRIA9, SRIA8, SRIA7, SRIA6, SRIA5, SRIA4
, SRIA3, SRIA2, SRIA1, SRIA0, SRIB17, SRIB16, SRIB15, SRIB14, SRIB13, SRIB12, SRIB11, SRIB10, SRIB9, SRIB8, SRIB7, SRIB6, SRIB5, SRIB4, SRIB3, SRIB2, SRIB1
, SRIB0, SROA17, SROA16, SROA15, SROA14, SROA13, SROA12, SROA11, SROA10, SROA9, SROA8, SROA7, SROA6, SROA5, SROA4, SROA3, SROA2, SROA1, SROA0, SROB17, SROB16
, SROB15, SROB14, SROB13, SROB12, SROB11, SROB10, SROB9, SROB8, SROB7, SROB6, SROB5, SROB4, SROB3, SROB2, SROB1, SROB0, ROA17, ROA16, ROA15, ROA14, ROA13
, ROA12, ROA11, ROA10, ROA9, ROA8, ROA7, ROA6, ROA5, ROA4, ROA3, ROA2, ROA1, ROA0, ROB17, ROB16, ROB15, ROB14, ROB13, ROB12, ROB11, ROB10
, ROB9, ROB8, ROB7, ROB6, ROB5, ROB4, ROB3, ROB2, ROB1, ROB0, ROC17, ROC16, ROC15, ROC14, ROC13, ROC12, ROC11, ROC10, ROC9, ROC8, ROC7
, ROC6, ROC5, ROC4, ROC3, ROC2, ROC1, ROC0, P35, P34, P33, P32, P31, P30, P29, P28, P27, P26, P25, P24, P23, P22
, P21, P20, P19, P18, P17, P16, P15, P14, P13, P12, P11, P10, P9, P8, P7, P6, P5, P4, P3, P2, P1
, P0, SIGNEDP);
parameter REG_INPUTA_CLK = "NONE";
parameter REG_INPUTA_CE = "CE0";
parameter REG_INPUTA_RST = "RST0";
@ -470,7 +486,28 @@ module MULT18X18D (...);
endmodule
(* blackbox *)
module ALU54B (...);
module ALU54B(CE3, CE2, CE1, CE0, CLK3, CLK2, CLK1, CLK0, RST3, RST2, RST1, RST0, SIGNEDIA, SIGNEDIB, SIGNEDCIN, A35, A34, A33, A32, A31, A30
, A29, A28, A27, A26, A25, A24, A23, A22, A21, A20, A19, A18, A17, A16, A15, A14, A13, A12, A11, A10, A9
, A8, A7, A6, A5, A4, A3, A2, A1, A0, B35, B34, B33, B32, B31, B30, B29, B28, B27, B26, B25, B24
, B23, B22, B21, B20, B19, B18, B17, B16, B15, B14, B13, B12, B11, B10, B9, B8, B7, B6, B5, B4, B3
, B2, B1, B0, C53, C52, C51, C50, C49, C48, C47, C46, C45, C44, C43, C42, C41, C40, C39, C38, C37, C36
, C35, C34, C33, C32, C31, C30, C29, C28, C27, C26, C25, C24, C23, C22, C21, C20, C19, C18, C17, C16, C15
, C14, C13, C12, C11, C10, C9, C8, C7, C6, C5, C4, C3, C2, C1, C0, CFB53, CFB52, CFB51, CFB50, CFB49, CFB48
, CFB47, CFB46, CFB45, CFB44, CFB43, CFB42, CFB41, CFB40, CFB39, CFB38, CFB37, CFB36, CFB35, CFB34, CFB33, CFB32, CFB31, CFB30, CFB29, CFB28, CFB27
, CFB26, CFB25, CFB24, CFB23, CFB22, CFB21, CFB20, CFB19, CFB18, CFB17, CFB16, CFB15, CFB14, CFB13, CFB12, CFB11, CFB10, CFB9, CFB8, CFB7, CFB6
, CFB5, CFB4, CFB3, CFB2, CFB1, CFB0, MA35, MA34, MA33, MA32, MA31, MA30, MA29, MA28, MA27, MA26, MA25, MA24, MA23, MA22, MA21
, MA20, MA19, MA18, MA17, MA16, MA15, MA14, MA13, MA12, MA11, MA10, MA9, MA8, MA7, MA6, MA5, MA4, MA3, MA2, MA1, MA0
, MB35, MB34, MB33, MB32, MB31, MB30, MB29, MB28, MB27, MB26, MB25, MB24, MB23, MB22, MB21, MB20, MB19, MB18, MB17, MB16, MB15
, MB14, MB13, MB12, MB11, MB10, MB9, MB8, MB7, MB6, MB5, MB4, MB3, MB2, MB1, MB0, CIN53, CIN52, CIN51, CIN50, CIN49, CIN48
, CIN47, CIN46, CIN45, CIN44, CIN43, CIN42, CIN41, CIN40, CIN39, CIN38, CIN37, CIN36, CIN35, CIN34, CIN33, CIN32, CIN31, CIN30, CIN29, CIN28, CIN27
, CIN26, CIN25, CIN24, CIN23, CIN22, CIN21, CIN20, CIN19, CIN18, CIN17, CIN16, CIN15, CIN14, CIN13, CIN12, CIN11, CIN10, CIN9, CIN8, CIN7, CIN6
, CIN5, CIN4, CIN3, CIN2, CIN1, CIN0, OP10, OP9, OP8, OP7, OP6, OP5, OP4, OP3, OP2, OP1, OP0, R53, R52, R51, R50
, R49, R48, R47, R46, R45, R44, R43, R42, R41, R40, R39, R38, R37, R36, R35, R34, R33, R32, R31, R30, R29
, R28, R27, R26, R25, R24, R23, R22, R21, R20, R19, R18, R17, R16, R15, R14, R13, R12, R11, R10, R9, R8
, R7, R6, R5, R4, R3, R2, R1, R0, CO53, CO52, CO51, CO50, CO49, CO48, CO47, CO46, CO45, CO44, CO43, CO42, CO41
, CO40, CO39, CO38, CO37, CO36, CO35, CO34, CO33, CO32, CO31, CO30, CO29, CO28, CO27, CO26, CO25, CO24, CO23, CO22, CO21, CO20
, CO19, CO18, CO17, CO16, CO15, CO14, CO13, CO12, CO11, CO10, CO9, CO8, CO7, CO6, CO5, CO4, CO3, CO2, CO1, CO0, EQZ
, EQZM, EQOM, EQPAT, EQPATB, OVER, UNDER, OVERUNDER, SIGNEDR);
parameter REG_INPUTC0_CLK = "NONE";
parameter REG_INPUTC0_CE = "CE0";
parameter REG_INPUTC0_RST = "RST0";
@ -970,7 +1007,7 @@ module ALU54B (...);
endmodule
(* blackbox *)
module CLKDIVF (...);
module CLKDIVF(CLKI, RST, ALIGNWD, CDIVX);
parameter GSR = "DISABLED";
parameter DIV = "2.0";
input CLKI;
@ -980,7 +1017,7 @@ module CLKDIVF (...);
endmodule
(* blackbox *)
module PCSCLKDIV (...);
module PCSCLKDIV(CLKI, RST, SEL2, SEL1, SEL0, CDIV1, CDIVX);
parameter GSR = "DISABLED";
input CLKI;
input RST;
@ -992,7 +1029,7 @@ module PCSCLKDIV (...);
endmodule
(* blackbox *)
module DCSC (...);
module DCSC(CLK1, CLK0, SEL1, SEL0, MODESEL, DCSOUT);
parameter DCSMODE = "POS";
input CLK1;
input CLK0;
@ -1003,21 +1040,21 @@ module DCSC (...);
endmodule
(* blackbox *)
module DCCA (...);
module DCCA(CLKI, CE, CLKO);
input CLKI;
input CE;
output CLKO;
endmodule
(* blackbox *)
module ECLKSYNCB (...);
module ECLKSYNCB(ECLKI, STOP, ECLKO);
input ECLKI;
input STOP;
output ECLKO;
endmodule
(* blackbox *)
module ECLKBRIDGECS (...);
module ECLKBRIDGECS(CLK0, CLK1, SEL, ECSOUT);
input CLK0;
input CLK1;
input SEL;
@ -1025,7 +1062,7 @@ module ECLKBRIDGECS (...);
endmodule
(* blackbox *)
module DELAYF (...);
module DELAYF(A, LOADN, MOVE, DIRECTION, Z, CFLAG);
parameter DEL_MODE = "USER_DEFINED";
parameter DEL_VALUE = 0;
input A;
@ -1037,7 +1074,7 @@ module DELAYF (...);
endmodule
(* blackbox *)
module DELAYG (...);
module DELAYG(A, Z);
parameter DEL_MODE = "USER_DEFINED";
parameter DEL_VALUE = 0;
input A;
@ -1045,13 +1082,14 @@ module DELAYG (...);
endmodule
(* blackbox *) (* keep *)
module USRMCLK (...);
module USRMCLK(USRMCLKI, USRMCLKTS);
input USRMCLKI;
input USRMCLKTS;
endmodule
(* blackbox *)
module DQSBUFM (...);
module DQSBUFM(DQSI, READ1, READ0, READCLKSEL2, READCLKSEL1, READCLKSEL0, DDRDEL, ECLK, SCLK, RST, DYNDELAY7, DYNDELAY6, DYNDELAY5, DYNDELAY4, DYNDELAY3, DYNDELAY2, DYNDELAY1, DYNDELAY0, PAUSE, RDLOADN, RDMOVE
, RDDIRECTION, WRLOADN, WRMOVE, WRDIRECTION, DQSR90, DQSW, DQSW270, RDPNTR2, RDPNTR1, RDPNTR0, WRPNTR2, WRPNTR1, WRPNTR0, DATAVALID, BURSTDET, RDCFLAG, WRCFLAG);
parameter DQS_LI_DEL_VAL = 4;
parameter DQS_LI_DEL_ADJ = "FACTORYONLY";
parameter DQS_LO_DEL_VAL = 0;
@ -1098,7 +1136,7 @@ module DQSBUFM (...);
endmodule
(* blackbox *)
module DDRDLLA (...);
module DDRDLLA(CLK, RST, UDDCNTLN, FREEZE, DDRDEL, LOCK, DCNTL7, DCNTL6, DCNTL5, DCNTL4, DCNTL3, DCNTL2, DCNTL1, DCNTL0);
parameter FORCE_MAX_DELAY = "NO";
parameter GSR = "ENABLED";
input CLK;
@ -1118,7 +1156,7 @@ module DDRDLLA (...);
endmodule
(* blackbox *)
module DLLDELD (...);
module DLLDELD(A, DDRDEL, LOADN, MOVE, DIRECTION, Z, CFLAG);
input A;
input DDRDEL;
input LOADN;
@ -1129,7 +1167,7 @@ module DLLDELD (...);
endmodule
(* blackbox *)
module IDDRX1F (...);
module IDDRX1F(D, SCLK, RST, Q0, Q1);
parameter GSR = "ENABLED";
input D;
input SCLK;
@ -1139,7 +1177,7 @@ module IDDRX1F (...);
endmodule
(* blackbox *)
module IDDRX2F (...);
module IDDRX2F(D, SCLK, ECLK, RST, ALIGNWD, Q3, Q2, Q1, Q0);
parameter GSR = "ENABLED";
input D;
input SCLK;
@ -1153,7 +1191,7 @@ module IDDRX2F (...);
endmodule
(* blackbox *)
module IDDR71B (...);
module IDDR71B(D, SCLK, ECLK, RST, ALIGNWD, Q6, Q5, Q4, Q3, Q2, Q1, Q0);
parameter GSR = "ENABLED";
input D;
input SCLK;
@ -1170,7 +1208,7 @@ module IDDR71B (...);
endmodule
(* blackbox *)
module IDDRX2DQA (...);
module IDDRX2DQA(SCLK, ECLK, DQSR90, D, RST, RDPNTR2, RDPNTR1, RDPNTR0, WRPNTR2, WRPNTR1, WRPNTR0, Q3, Q2, Q1, Q0, QWL);
parameter GSR = "ENABLED";
input SCLK;
input ECLK;
@ -1191,7 +1229,7 @@ module IDDRX2DQA (...);
endmodule
(* blackbox *)
module ODDRX1F (...);
module ODDRX1F(SCLK, RST, D0, D1, Q);
parameter GSR = "ENABLED";
input SCLK;
input RST;
@ -1201,7 +1239,7 @@ module ODDRX1F (...);
endmodule
(* blackbox *)
module ODDRX2F (...);
module ODDRX2F(SCLK, ECLK, RST, D3, D2, D1, D0, Q);
parameter GSR = "ENABLED";
input SCLK;
input ECLK;
@ -1214,7 +1252,7 @@ module ODDRX2F (...);
endmodule
(* blackbox *)
module ODDR71B (...);
module ODDR71B(SCLK, ECLK, RST, D6, D5, D4, D3, D2, D1, D0, Q);
parameter GSR = "ENABLED";
input SCLK;
input ECLK;
@ -1230,7 +1268,7 @@ module ODDR71B (...);
endmodule
(* blackbox *)
module OSHX2A (...);
module OSHX2A(D1, D0, SCLK, ECLK, RST, Q);
parameter GSR = "ENABLED";
input D1;
input D0;
@ -1241,7 +1279,7 @@ module OSHX2A (...);
endmodule
(* blackbox *)
module TSHX2DQA (...);
module TSHX2DQA(T1, T0, SCLK, ECLK, DQSW270, RST, Q);
parameter GSR = "ENABLED";
parameter REGSET = "SET";
input T1;
@ -1254,7 +1292,7 @@ module TSHX2DQA (...);
endmodule
(* blackbox *)
module TSHX2DQSA (...);
module TSHX2DQSA(T1, T0, SCLK, ECLK, DQSW, RST, Q);
parameter GSR = "ENABLED";
parameter REGSET = "SET";
input T1;
@ -1267,7 +1305,7 @@ module TSHX2DQSA (...);
endmodule
(* blackbox *)
module ODDRX2DQA (...);
module ODDRX2DQA(D3, D2, D1, D0, DQSW270, SCLK, ECLK, RST, Q);
parameter GSR = "ENABLED";
input D3;
input D2;
@ -1281,7 +1319,7 @@ module ODDRX2DQA (...);
endmodule
(* blackbox *)
module ODDRX2DQSB (...);
module ODDRX2DQSB(D3, D2, D1, D0, SCLK, ECLK, DQSW, RST, Q);
parameter GSR = "ENABLED";
input D3;
input D2;
@ -1295,7 +1333,8 @@ module ODDRX2DQSB (...);
endmodule
(* blackbox *)
module EHXPLLL (...);
module EHXPLLL(CLKI, CLKFB, PHASESEL1, PHASESEL0, PHASEDIR, PHASESTEP, PHASELOADREG, STDBY, PLLWAKESYNC, RST, ENCLKOP, ENCLKOS, ENCLKOS2, ENCLKOS3, CLKOP, CLKOS, CLKOS2, CLKOS3, LOCK, INTLOCK, REFCLK
, CLKINTFB);
parameter CLKI_DIV = 1;
parameter CLKFB_DIV = 1;
parameter CLKOP_DIV = 8;
@ -1357,7 +1396,7 @@ module EHXPLLL (...);
endmodule
(* blackbox *)
module DTR (...);
module DTR(STARTPULSE, DTROUT7, DTROUT6, DTROUT5, DTROUT4, DTROUT3, DTROUT2, DTROUT1, DTROUT0);
parameter DTR_TEMP = 25;
input STARTPULSE;
output DTROUT7;
@ -1371,13 +1410,13 @@ module DTR (...);
endmodule
(* blackbox *)
module OSCG (...);
module OSCG(OSC);
parameter DIV = 128;
output OSC;
endmodule
(* blackbox *)
module EXTREFB (...);
module EXTREFB(REFCLKP, REFCLKN, REFCLKO);
parameter REFCK_PWDNB = "DONTCARE";
parameter REFCK_RTERM = "DONTCARE";
parameter REFCK_DCBIAS_EN = "DONTCARE";
@ -1389,7 +1428,7 @@ module EXTREFB (...);
endmodule
(* blackbox *) (* keep *)
module JTAGG (...);
module JTAGG(TCK, TMS, TDI, JTDO2, JTDO1, TDO, JTDI, JTCK, JRTI2, JRTI1, JSHIFT, JUPDATE, JRSTN, JCE2, JCE1);
parameter ER1 = "ENABLED";
parameter ER2 = "ENABLED";
(* iopad_external_pin *)
@ -1414,7 +1453,20 @@ module JTAGG (...);
endmodule
(* blackbox *) (* keep *)
module DCUA (...);
module DCUA(CH0_HDINP, CH1_HDINP, CH0_HDINN, CH1_HDINN, D_TXBIT_CLKP_FROM_ND, D_TXBIT_CLKN_FROM_ND, D_SYNC_ND, D_TXPLL_LOL_FROM_ND, CH0_RX_REFCLK, CH1_RX_REFCLK, CH0_FF_RXI_CLK, CH1_FF_RXI_CLK, CH0_FF_TXI_CLK, CH1_FF_TXI_CLK, CH0_FF_EBRD_CLK, CH1_FF_EBRD_CLK, CH0_FF_TX_D_0, CH1_FF_TX_D_0, CH0_FF_TX_D_1, CH1_FF_TX_D_1, CH0_FF_TX_D_2
, CH1_FF_TX_D_2, CH0_FF_TX_D_3, CH1_FF_TX_D_3, CH0_FF_TX_D_4, CH1_FF_TX_D_4, CH0_FF_TX_D_5, CH1_FF_TX_D_5, CH0_FF_TX_D_6, CH1_FF_TX_D_6, CH0_FF_TX_D_7, CH1_FF_TX_D_7, CH0_FF_TX_D_8, CH1_FF_TX_D_8, CH0_FF_TX_D_9, CH1_FF_TX_D_9, CH0_FF_TX_D_10, CH1_FF_TX_D_10, CH0_FF_TX_D_11, CH1_FF_TX_D_11, CH0_FF_TX_D_12, CH1_FF_TX_D_12
, CH0_FF_TX_D_13, CH1_FF_TX_D_13, CH0_FF_TX_D_14, CH1_FF_TX_D_14, CH0_FF_TX_D_15, CH1_FF_TX_D_15, CH0_FF_TX_D_16, CH1_FF_TX_D_16, CH0_FF_TX_D_17, CH1_FF_TX_D_17, CH0_FF_TX_D_18, CH1_FF_TX_D_18, CH0_FF_TX_D_19, CH1_FF_TX_D_19, CH0_FF_TX_D_20, CH1_FF_TX_D_20, CH0_FF_TX_D_21, CH1_FF_TX_D_21, CH0_FF_TX_D_22, CH1_FF_TX_D_22, CH0_FF_TX_D_23
, CH1_FF_TX_D_23, CH0_FFC_EI_EN, CH1_FFC_EI_EN, CH0_FFC_PCIE_DET_EN, CH1_FFC_PCIE_DET_EN, CH0_FFC_PCIE_CT, CH1_FFC_PCIE_CT, CH0_FFC_SB_INV_RX, CH1_FFC_SB_INV_RX, CH0_FFC_ENABLE_CGALIGN, CH1_FFC_ENABLE_CGALIGN, CH0_FFC_SIGNAL_DETECT, CH1_FFC_SIGNAL_DETECT, CH0_FFC_FB_LOOPBACK, CH1_FFC_FB_LOOPBACK, CH0_FFC_SB_PFIFO_LP, CH1_FFC_SB_PFIFO_LP, CH0_FFC_PFIFO_CLR, CH1_FFC_PFIFO_CLR, CH0_FFC_RATE_MODE_RX, CH1_FFC_RATE_MODE_RX
, CH0_FFC_RATE_MODE_TX, CH1_FFC_RATE_MODE_TX, CH0_FFC_DIV11_MODE_RX, CH1_FFC_DIV11_MODE_RX, CH0_FFC_RX_GEAR_MODE, CH1_FFC_RX_GEAR_MODE, CH0_FFC_TX_GEAR_MODE, CH1_FFC_TX_GEAR_MODE, CH0_FFC_DIV11_MODE_TX, CH1_FFC_DIV11_MODE_TX, CH0_FFC_LDR_CORE2TX_EN, CH1_FFC_LDR_CORE2TX_EN, CH0_FFC_LANE_TX_RST, CH1_FFC_LANE_TX_RST, CH0_FFC_LANE_RX_RST, CH1_FFC_LANE_RX_RST, CH0_FFC_RRST, CH1_FFC_RRST, CH0_FFC_TXPWDNB, CH1_FFC_TXPWDNB, CH0_FFC_RXPWDNB
, CH1_FFC_RXPWDNB, CH0_LDR_CORE2TX, CH1_LDR_CORE2TX, D_SCIWDATA0, D_SCIWDATA1, D_SCIWDATA2, D_SCIWDATA3, D_SCIWDATA4, D_SCIWDATA5, D_SCIWDATA6, D_SCIWDATA7, D_SCIADDR0, D_SCIADDR1, D_SCIADDR2, D_SCIADDR3, D_SCIADDR4, D_SCIADDR5, D_SCIENAUX, D_SCISELAUX, CH0_SCIEN, CH1_SCIEN
, CH0_SCISEL, CH1_SCISEL, D_SCIRD, D_SCIWSTN, D_CYAWSTN, D_FFC_SYNC_TOGGLE, D_FFC_DUAL_RST, D_FFC_MACRO_RST, D_FFC_MACROPDB, D_FFC_TRST, CH0_FFC_CDR_EN_BITSLIP, CH1_FFC_CDR_EN_BITSLIP, D_SCAN_ENABLE, D_SCAN_IN_0, D_SCAN_IN_1, D_SCAN_IN_2, D_SCAN_IN_3, D_SCAN_IN_4, D_SCAN_IN_5, D_SCAN_IN_6, D_SCAN_IN_7
, D_SCAN_MODE, D_SCAN_RESET, D_CIN0, D_CIN1, D_CIN2, D_CIN3, D_CIN4, D_CIN5, D_CIN6, D_CIN7, D_CIN8, D_CIN9, D_CIN10, D_CIN11, CH0_HDOUTP, CH1_HDOUTP, CH0_HDOUTN, CH1_HDOUTN, D_TXBIT_CLKP_TO_ND, D_TXBIT_CLKN_TO_ND, D_SYNC_PULSE2ND
, D_TXPLL_LOL_TO_ND, CH0_FF_RX_F_CLK, CH1_FF_RX_F_CLK, CH0_FF_RX_H_CLK, CH1_FF_RX_H_CLK, CH0_FF_TX_F_CLK, CH1_FF_TX_F_CLK, CH0_FF_TX_H_CLK, CH1_FF_TX_H_CLK, CH0_FF_RX_PCLK, CH1_FF_RX_PCLK, CH0_FF_TX_PCLK, CH1_FF_TX_PCLK, CH0_FF_RX_D_0, CH1_FF_RX_D_0, CH0_FF_RX_D_1, CH1_FF_RX_D_1, CH0_FF_RX_D_2, CH1_FF_RX_D_2, CH0_FF_RX_D_3, CH1_FF_RX_D_3
, CH0_FF_RX_D_4, CH1_FF_RX_D_4, CH0_FF_RX_D_5, CH1_FF_RX_D_5, CH0_FF_RX_D_6, CH1_FF_RX_D_6, CH0_FF_RX_D_7, CH1_FF_RX_D_7, CH0_FF_RX_D_8, CH1_FF_RX_D_8, CH0_FF_RX_D_9, CH1_FF_RX_D_9, CH0_FF_RX_D_10, CH1_FF_RX_D_10, CH0_FF_RX_D_11, CH1_FF_RX_D_11, CH0_FF_RX_D_12, CH1_FF_RX_D_12, CH0_FF_RX_D_13, CH1_FF_RX_D_13, CH0_FF_RX_D_14
, CH1_FF_RX_D_14, CH0_FF_RX_D_15, CH1_FF_RX_D_15, CH0_FF_RX_D_16, CH1_FF_RX_D_16, CH0_FF_RX_D_17, CH1_FF_RX_D_17, CH0_FF_RX_D_18, CH1_FF_RX_D_18, CH0_FF_RX_D_19, CH1_FF_RX_D_19, CH0_FF_RX_D_20, CH1_FF_RX_D_20, CH0_FF_RX_D_21, CH1_FF_RX_D_21, CH0_FF_RX_D_22, CH1_FF_RX_D_22, CH0_FF_RX_D_23, CH1_FF_RX_D_23, CH0_FFS_PCIE_DONE, CH1_FFS_PCIE_DONE
, CH0_FFS_PCIE_CON, CH1_FFS_PCIE_CON, CH0_FFS_RLOS, CH1_FFS_RLOS, CH0_FFS_LS_SYNC_STATUS, CH1_FFS_LS_SYNC_STATUS, CH0_FFS_CC_UNDERRUN, CH1_FFS_CC_UNDERRUN, CH0_FFS_CC_OVERRUN, CH1_FFS_CC_OVERRUN, CH0_FFS_RXFBFIFO_ERROR, CH1_FFS_RXFBFIFO_ERROR, CH0_FFS_TXFBFIFO_ERROR, CH1_FFS_TXFBFIFO_ERROR, CH0_FFS_RLOL, CH1_FFS_RLOL, CH0_FFS_SKP_ADDED, CH1_FFS_SKP_ADDED, CH0_FFS_SKP_DELETED, CH1_FFS_SKP_DELETED, CH0_LDR_RX2CORE
, CH1_LDR_RX2CORE, D_SCIRDATA0, D_SCIRDATA1, D_SCIRDATA2, D_SCIRDATA3, D_SCIRDATA4, D_SCIRDATA5, D_SCIRDATA6, D_SCIRDATA7, D_SCIINT, D_SCAN_OUT_0, D_SCAN_OUT_1, D_SCAN_OUT_2, D_SCAN_OUT_3, D_SCAN_OUT_4, D_SCAN_OUT_5, D_SCAN_OUT_6, D_SCAN_OUT_7, D_COUT0, D_COUT1, D_COUT2
, D_COUT3, D_COUT4, D_COUT5, D_COUT6, D_COUT7, D_COUT8, D_COUT9, D_COUT10, D_COUT11, D_COUT12, D_COUT13, D_COUT14, D_COUT15, D_COUT16, D_COUT17, D_COUT18, D_COUT19, D_REFCLKI, D_FFS_PLOL);
parameter D_MACROPDB = "DONTCARE";
parameter D_IB_PWDNB = "DONTCARE";
parameter D_XGE_MODE = "DONTCARE";

469
techlibs/lattice/cells_bb_nexus.v
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File diff suppressed because it is too large Load diff

41
techlibs/lattice/cells_bb_xo2.v
View file

@ -1,18 +1,21 @@
// Created by cells_xtra.py from Lattice models
(* blackbox *) (* keep *)
module GSR (...);
module GSR(GSR);
input GSR;
endmodule
(* blackbox *) (* keep *)
module SGSR (...);
module SGSR(GSR, CLK);
input GSR;
input CLK;
endmodule
(* blackbox *)
module DP8KC (...);
module DP8KC(DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, ADA2, ADA1
, ADA0, CEA, OCEA, CLKA, WEA, CSA2, CSA1, CSA0, RSTA, DIB8, DIB7, DIB6, DIB5, DIB4, DIB3, DIB2, DIB1, DIB0, ADB12, ADB11, ADB10
, ADB9, ADB8, ADB7, ADB6, ADB5, ADB4, ADB3, ADB2, ADB1, ADB0, CEB, OCEB, CLKB, WEB, CSB2, CSB1, CSB0, RSTB, DOA8, DOA7, DOA6
, DOA5, DOA4, DOA3, DOA2, DOA1, DOA0, DOB8, DOB7, DOB6, DOB5, DOB4, DOB3, DOB2, DOB1, DOB0);
parameter DATA_WIDTH_A = 9;
parameter DATA_WIDTH_B = 9;
parameter REGMODE_A = "NOREG";
@ -138,7 +141,10 @@ module DP8KC (...);
endmodule
(* blackbox *)
module PDPW8KC (...);
module PDPW8KC(DI17, DI16, DI15, DI14, DI13, DI12, DI11, DI10, DI9, DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0, ADW8, ADW7, ADW6
, ADW5, ADW4, ADW3, ADW2, ADW1, ADW0, BE1, BE0, CEW, CLKW, CSW2, CSW1, CSW0, ADR12, ADR11, ADR10, ADR9, ADR8, ADR7, ADR6, ADR5
, ADR4, ADR3, ADR2, ADR1, ADR0, CER, OCER, CLKR, CSR2, CSR1, CSR0, RST, DO17, DO16, DO15, DO14, DO13, DO12, DO11, DO10, DO9
, DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0);
parameter DATA_WIDTH_W = 18;
parameter DATA_WIDTH_R = 9;
parameter REGMODE = "NOREG";
@ -255,7 +261,8 @@ module PDPW8KC (...);
endmodule
(* blackbox *)
module SP8KC (...);
module SP8KC(DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0, AD12, AD11, AD10, AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1
, AD0, CE, OCE, CLK, WE, CS2, CS1, CS0, RST, DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0);
parameter DATA_WIDTH = 9;
parameter REGMODE = "NOREG";
parameter CSDECODE = "0b000";
@ -338,7 +345,9 @@ module SP8KC (...);
endmodule
(* blackbox *)
module FIFO8KB (...);
module FIFO8KB(DI0, DI1, DI2, DI3, DI4, DI5, DI6, DI7, DI8, DI9, DI10, DI11, DI12, DI13, DI14, DI15, DI16, DI17, CSW0, CSW1, CSR0
, CSR1, WE, RE, ORE, CLKW, CLKR, RST, RPRST, FULLI, EMPTYI, DO0, DO1, DO2, DO3, DO4, DO5, DO6, DO7, DO8, DO9, DO10
, DO11, DO12, DO13, DO14, DO15, DO16, DO17, EF, AEF, AFF, FF);
parameter DATA_WIDTH_W = 18;
parameter DATA_WIDTH_R = 18;
parameter REGMODE = "NOREG";
@ -409,7 +418,7 @@ module FIFO8KB (...);
endmodule
(* blackbox *)
module CLKDIVC (...);
module CLKDIVC(RST, CLKI, ALIGNWD, CDIV1, CDIVX);
parameter GSR = "DISABLED";
parameter DIV = "2.0";
input RST;
@ -420,7 +429,7 @@ module CLKDIVC (...);
endmodule
(* blackbox *)
module DCMA (...);
module DCMA(CLK0, CLK1, SEL, DCMOUT);
input CLK0;
input CLK1;
input SEL;
@ -428,14 +437,14 @@ module DCMA (...);
endmodule
(* blackbox *)
module ECLKSYNCA (...);
module ECLKSYNCA(ECLKI, STOP, ECLKO);
input ECLKI;
input STOP;
output ECLKO;
endmodule
(* blackbox *)
module ECLKBRIDGECS (...);
module ECLKBRIDGECS(CLK0, CLK1, SEL, ECSOUT);
input CLK0;
input CLK1;
input SEL;
@ -443,19 +452,21 @@ module ECLKBRIDGECS (...);
endmodule
(* blackbox *)
module DCCA (...);
module DCCA(CLKI, CE, CLKO);
input CLKI;
input CE;
output CLKO;
endmodule
(* blackbox *) (* keep *)
module START (...);
module START(STARTCLK);
input STARTCLK;
endmodule
(* blackbox *)
module EHXPLLJ (...);
module EHXPLLJ(CLKI, CLKFB, PHASESEL1, PHASESEL0, PHASEDIR, PHASESTEP, LOADREG, STDBY, PLLWAKESYNC, RST, RESETM, RESETC, RESETD, ENCLKOP, ENCLKOS, ENCLKOS2, ENCLKOS3, PLLCLK, PLLRST, PLLSTB, PLLWE
, PLLDATI7, PLLDATI6, PLLDATI5, PLLDATI4, PLLDATI3, PLLDATI2, PLLDATI1, PLLDATI0, PLLADDR4, PLLADDR3, PLLADDR2, PLLADDR1, PLLADDR0, CLKOP, CLKOS, CLKOS2, CLKOS3, LOCK, INTLOCK, REFCLK, PLLDATO7
, PLLDATO6, PLLDATO5, PLLDATO4, PLLDATO3, PLLDATO2, PLLDATO1, PLLDATO0, PLLACK, DPHSRC, CLKINTFB);
parameter CLKI_DIV = 1;
parameter CLKFB_DIV = 1;
parameter CLKOP_DIV = 8;
@ -557,7 +568,7 @@ module EHXPLLJ (...);
endmodule
(* blackbox *)
module OSCH (...);
module OSCH(STDBY, OSC, SEDSTDBY);
parameter NOM_FREQ = "2.08";
input STDBY;
output OSC;
@ -565,7 +576,7 @@ module OSCH (...);
endmodule
(* blackbox *) (* keep *)
module TSALL (...);
module TSALL(TSALL);
input TSALL;
endmodule

41
techlibs/lattice/cells_bb_xo3.v
View file

@ -1,18 +1,21 @@
// Created by cells_xtra.py from Lattice models
(* blackbox *) (* keep *)
module GSR (...);
module GSR(GSR);
input GSR;
endmodule
(* blackbox *) (* keep *)
module SGSR (...);
module SGSR(GSR, CLK);
input GSR;
input CLK;
endmodule
(* blackbox *)
module DP8KC (...);
module DP8KC(DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, ADA2, ADA1
, ADA0, CEA, OCEA, CLKA, WEA, CSA2, CSA1, CSA0, RSTA, DIB8, DIB7, DIB6, DIB5, DIB4, DIB3, DIB2, DIB1, DIB0, ADB12, ADB11, ADB10
, ADB9, ADB8, ADB7, ADB6, ADB5, ADB4, ADB3, ADB2, ADB1, ADB0, CEB, OCEB, CLKB, WEB, CSB2, CSB1, CSB0, RSTB, DOA8, DOA7, DOA6
, DOA5, DOA4, DOA3, DOA2, DOA1, DOA0, DOB8, DOB7, DOB6, DOB5, DOB4, DOB3, DOB2, DOB1, DOB0);
parameter DATA_WIDTH_A = 9;
parameter DATA_WIDTH_B = 9;
parameter REGMODE_A = "NOREG";
@ -138,7 +141,10 @@ module DP8KC (...);
endmodule
(* blackbox *)
module PDPW8KC (...);
module PDPW8KC(DI17, DI16, DI15, DI14, DI13, DI12, DI11, DI10, DI9, DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0, ADW8, ADW7, ADW6
, ADW5, ADW4, ADW3, ADW2, ADW1, ADW0, BE1, BE0, CEW, CLKW, CSW2, CSW1, CSW0, ADR12, ADR11, ADR10, ADR9, ADR8, ADR7, ADR6, ADR5
, ADR4, ADR3, ADR2, ADR1, ADR0, CER, OCER, CLKR, CSR2, CSR1, CSR0, RST, DO17, DO16, DO15, DO14, DO13, DO12, DO11, DO10, DO9
, DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0);
parameter DATA_WIDTH_W = 18;
parameter DATA_WIDTH_R = 9;
parameter REGMODE = "NOREG";
@ -255,7 +261,8 @@ module PDPW8KC (...);
endmodule
(* blackbox *)
module SP8KC (...);
module SP8KC(DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0, AD12, AD11, AD10, AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1
, AD0, CE, OCE, CLK, WE, CS2, CS1, CS0, RST, DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0);
parameter DATA_WIDTH = 9;
parameter REGMODE = "NOREG";
parameter CSDECODE = "0b000";
@ -338,7 +345,9 @@ module SP8KC (...);
endmodule
(* blackbox *)
module FIFO8KB (...);
module FIFO8KB(DI0, DI1, DI2, DI3, DI4, DI5, DI6, DI7, DI8, DI9, DI10, DI11, DI12, DI13, DI14, DI15, DI16, DI17, CSW0, CSW1, CSR0
, CSR1, WE, RE, ORE, CLKW, CLKR, RST, RPRST, FULLI, EMPTYI, DO0, DO1, DO2, DO3, DO4, DO5, DO6, DO7, DO8, DO9, DO10
, DO11, DO12, DO13, DO14, DO15, DO16, DO17, EF, AEF, AFF, FF);
parameter DATA_WIDTH_W = 18;
parameter DATA_WIDTH_R = 18;
parameter REGMODE = "NOREG";
@ -409,7 +418,7 @@ module FIFO8KB (...);
endmodule
(* blackbox *)
module CLKDIVC (...);
module CLKDIVC(RST, CLKI, ALIGNWD, CDIV1, CDIVX);
parameter GSR = "DISABLED";
parameter DIV = "2.0";
input RST;
@ -420,7 +429,7 @@ module CLKDIVC (...);
endmodule
(* blackbox *)
module DCMA (...);
module DCMA(CLK0, CLK1, SEL, DCMOUT);
input CLK0;
input CLK1;
input SEL;
@ -428,14 +437,14 @@ module DCMA (...);
endmodule
(* blackbox *)
module ECLKSYNCA (...);
module ECLKSYNCA(ECLKI, STOP, ECLKO);
input ECLKI;
input STOP;
output ECLKO;
endmodule
(* blackbox *)
module ECLKBRIDGECS (...);
module ECLKBRIDGECS(CLK0, CLK1, SEL, ECSOUT);
input CLK0;
input CLK1;
input SEL;
@ -443,19 +452,21 @@ module ECLKBRIDGECS (...);
endmodule
(* blackbox *)
module DCCA (...);
module DCCA(CLKI, CE, CLKO);
input CLKI;
input CE;
output CLKO;
endmodule
(* blackbox *) (* keep *)
module START (...);
module START(STARTCLK);
input STARTCLK;
endmodule
(* blackbox *)
module EHXPLLJ (...);
module EHXPLLJ(CLKI, CLKFB, PHASESEL1, PHASESEL0, PHASEDIR, PHASESTEP, LOADREG, STDBY, PLLWAKESYNC, RST, RESETM, RESETC, RESETD, ENCLKOP, ENCLKOS, ENCLKOS2, ENCLKOS3, PLLCLK, PLLRST, PLLSTB, PLLWE
, PLLDATI7, PLLDATI6, PLLDATI5, PLLDATI4, PLLDATI3, PLLDATI2, PLLDATI1, PLLDATI0, PLLADDR4, PLLADDR3, PLLADDR2, PLLADDR1, PLLADDR0, CLKOP, CLKOS, CLKOS2, CLKOS3, LOCK, INTLOCK, REFCLK, PLLDATO7
, PLLDATO6, PLLDATO5, PLLDATO4, PLLDATO3, PLLDATO2, PLLDATO1, PLLDATO0, PLLACK, DPHSRC, CLKINTFB);
parameter CLKI_DIV = 1;
parameter CLKFB_DIV = 1;
parameter CLKOP_DIV = 8;
@ -557,7 +568,7 @@ module EHXPLLJ (...);
endmodule
(* blackbox *)
module OSCH (...);
module OSCH(STDBY, OSC, SEDSTDBY);
parameter NOM_FREQ = "2.08";
input STDBY;
output OSC;
@ -565,7 +576,7 @@ module OSCH (...);
endmodule
(* blackbox *) (* keep *)
module TSALL (...);
module TSALL(TSALL);
input TSALL;
endmodule

41
techlibs/lattice/cells_bb_xo3d.v
View file

@ -1,18 +1,21 @@
// Created by cells_xtra.py from Lattice models
(* blackbox *) (* keep *)
module GSR (...);
module GSR(GSR);
input GSR;
endmodule
(* blackbox *) (* keep *)
module SGSR (...);
module SGSR(GSR, CLK);
input GSR;
input CLK;
endmodule
(* blackbox *)
module DP8KC (...);
module DP8KC(DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, ADA2, ADA1
, ADA0, CEA, OCEA, CLKA, WEA, CSA2, CSA1, CSA0, RSTA, DIB8, DIB7, DIB6, DIB5, DIB4, DIB3, DIB2, DIB1, DIB0, ADB12, ADB11, ADB10
, ADB9, ADB8, ADB7, ADB6, ADB5, ADB4, ADB3, ADB2, ADB1, ADB0, CEB, OCEB, CLKB, WEB, CSB2, CSB1, CSB0, RSTB, DOA8, DOA7, DOA6
, DOA5, DOA4, DOA3, DOA2, DOA1, DOA0, DOB8, DOB7, DOB6, DOB5, DOB4, DOB3, DOB2, DOB1, DOB0);
parameter DATA_WIDTH_A = 9;
parameter DATA_WIDTH_B = 9;
parameter REGMODE_A = "NOREG";
@ -138,7 +141,10 @@ module DP8KC (...);
endmodule
(* blackbox *)
module PDPW8KC (...);
module PDPW8KC(DI17, DI16, DI15, DI14, DI13, DI12, DI11, DI10, DI9, DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0, ADW8, ADW7, ADW6
, ADW5, ADW4, ADW3, ADW2, ADW1, ADW0, BE1, BE0, CEW, CLKW, CSW2, CSW1, CSW0, ADR12, ADR11, ADR10, ADR9, ADR8, ADR7, ADR6, ADR5
, ADR4, ADR3, ADR2, ADR1, ADR0, CER, OCER, CLKR, CSR2, CSR1, CSR0, RST, DO17, DO16, DO15, DO14, DO13, DO12, DO11, DO10, DO9
, DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0);
parameter DATA_WIDTH_W = 18;
parameter DATA_WIDTH_R = 9;
parameter REGMODE = "NOREG";
@ -255,7 +261,8 @@ module PDPW8KC (...);
endmodule
(* blackbox *)
module SP8KC (...);
module SP8KC(DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0, AD12, AD11, AD10, AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1
, AD0, CE, OCE, CLK, WE, CS2, CS1, CS0, RST, DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0);
parameter DATA_WIDTH = 9;
parameter REGMODE = "NOREG";
parameter CSDECODE = "0b000";
@ -338,7 +345,9 @@ module SP8KC (...);
endmodule
(* blackbox *)
module FIFO8KB (...);
module FIFO8KB(DI0, DI1, DI2, DI3, DI4, DI5, DI6, DI7, DI8, DI9, DI10, DI11, DI12, DI13, DI14, DI15, DI16, DI17, CSW0, CSW1, CSR0
, CSR1, WE, RE, ORE, CLKW, CLKR, RST, RPRST, FULLI, EMPTYI, DO0, DO1, DO2, DO3, DO4, DO5, DO6, DO7, DO8, DO9, DO10
, DO11, DO12, DO13, DO14, DO15, DO16, DO17, EF, AEF, AFF, FF);
parameter DATA_WIDTH_W = 18;
parameter DATA_WIDTH_R = 18;
parameter REGMODE = "NOREG";
@ -409,7 +418,7 @@ module FIFO8KB (...);
endmodule
(* blackbox *)
module CLKDIVC (...);
module CLKDIVC(RST, CLKI, ALIGNWD, CDIV1, CDIVX);
parameter GSR = "DISABLED";
parameter DIV = "2.0";
input RST;
@ -420,7 +429,7 @@ module CLKDIVC (...);
endmodule
(* blackbox *)
module DCMA (...);
module DCMA(CLK0, CLK1, SEL, DCMOUT);
input CLK0;
input CLK1;
input SEL;
@ -428,14 +437,14 @@ module DCMA (...);
endmodule
(* blackbox *)
module ECLKSYNCA (...);
module ECLKSYNCA(ECLKI, STOP, ECLKO);
input ECLKI;
input STOP;
output ECLKO;
endmodule
(* blackbox *)
module ECLKBRIDGECS (...);
module ECLKBRIDGECS(CLK0, CLK1, SEL, ECSOUT);
input CLK0;
input CLK1;
input SEL;
@ -443,19 +452,21 @@ module ECLKBRIDGECS (...);
endmodule
(* blackbox *)
module DCCA (...);
module DCCA(CLKI, CE, CLKO);
input CLKI;
input CE;
output CLKO;
endmodule
(* blackbox *) (* keep *)
module START (...);
module START(STARTCLK);
input STARTCLK;
endmodule
(* blackbox *)
module EHXPLLJ (...);
module EHXPLLJ(CLKI, CLKFB, PHASESEL1, PHASESEL0, PHASEDIR, PHASESTEP, LOADREG, STDBY, PLLWAKESYNC, RST, RESETM, RESETC, RESETD, ENCLKOP, ENCLKOS, ENCLKOS2, ENCLKOS3, PLLCLK, PLLRST, PLLSTB, PLLWE
, PLLDATI7, PLLDATI6, PLLDATI5, PLLDATI4, PLLDATI3, PLLDATI2, PLLDATI1, PLLDATI0, PLLADDR4, PLLADDR3, PLLADDR2, PLLADDR1, PLLADDR0, CLKOP, CLKOS, CLKOS2, CLKOS3, LOCK, INTLOCK, REFCLK, PLLDATO7
, PLLDATO6, PLLDATO5, PLLDATO4, PLLDATO3, PLLDATO2, PLLDATO1, PLLDATO0, PLLACK, DPHSRC, CLKINTFB);
parameter CLKI_DIV = 1;
parameter CLKFB_DIV = 1;
parameter CLKOP_DIV = 8;
@ -557,7 +568,7 @@ module EHXPLLJ (...);
endmodule
(* blackbox *)
module OSCJ (...);
module OSCJ(STDBY, OSC, SEDSTDBY, OSCESB);
parameter NOM_FREQ = "2.08";
input STDBY;
output OSC;
@ -566,7 +577,7 @@ module OSCJ (...);
endmodule
(* blackbox *) (* keep *)
module TSALL (...);
module TSALL(TSALL);
input TSALL;
endmodule

1365
techlibs/xilinx/cells_xtra.v
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