Akash Levy
2b247d165b
Merge from main
2026-02-13 04:14:08 -08:00
Miodrag Milanović
e4b32d6aae
Merge pull request #5670 from max-kudinov/gowin_mult
...
Gowin: Add DSP inference for GW1N and GW2A
2026-02-12 14:30:27 +01:00
Maxim Kudinov
5b94a97fb3
gowin: synth_gowin: Add -nodsp option
2026-02-12 13:58:47 +03:00
Maxim Kudinov
542b29fa6a
gowin: synth_gowin: Merge flatten label with coarse
2026-02-12 13:58:47 +03:00
Maxim Kudinov
5ea073d45e
gowin: format MULT instances
2026-02-12 13:35:49 +03:00
Gus Smith
e3db8fee6f
Merge pull request #3459 from gs-jgj/feature_dsp48e1_presub
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Add support for subtract in preadder
2026-02-11 08:02:18 -08:00
Akash Levy
f74ac17a5f
Undo the terrible upstream changes that break everything...
2026-02-04 22:26:06 -08:00
Akash Levy
d3ab45c2fa
Merge branch 'YosysHQ:main' into main
2026-02-04 15:53:43 -08:00
Emil J
992e64342c
Merge pull request #5621 from rocallahan/remove-opt-sort
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Remove `Design::sort()` calls from optimization passes
2026-02-04 16:55:56 +01:00
Jeppe Johansen
44afd4bbdd
Add support for subtraction in preadder
2026-02-03 08:31:01 -08:00
Akash Levy
a9cf998f9f
Merge from upstream
2026-01-29 17:46:44 -08:00
Krystine Sherwin
c3ffb48a6b
Add and use fix_mod.py
2026-01-28 07:45:58 +13:00
Maxim Kudinov
808ec8c04b
gowin: synth_gowin: Add MULT inference for GW1N and GW2A
2026-01-25 22:10:08 +03:00
Robert O'Callahan
e87bb65956
Move Design::sort() calls out of opt and opt_clean passes into the synth passes that need them.
2026-01-23 01:14:35 +00:00
Akash Levy
e332ba807d
Merge branch 'YosysHQ:main' into main
2026-01-07 12:40:39 -08:00
YRabbit
8a78f2f7c5
Gowin. Fix style.
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Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2026-01-05 20:07:31 +10:00
YRabbit
ea90f54783
Gowin. Implement byte enable.
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Enable write port with byte enables for BSRAM primitives.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2026-01-03 17:42:49 +10:00
Akash Levy
abd485fa49
Bump Yosys to latest
2025-12-17 21:06:17 -08:00
nataliakokoromyti
e289e4c893
add ID::src to allowlist instead
2025-12-17 01:31:32 -08:00
nataliakokoromyti
cf8be2bae7
Update ice40_wrapcarry.cc
2025-12-16 09:33:47 -08:00
Akash Levy
a705042d2e
Merge branch 'YosysHQ:main' into main
2025-11-20 23:05:40 -05:00
Emil J. Tywoniak
1edc32dcd0
opensta, sdc_expand: mark as experimental
2025-11-19 15:31:17 +01:00
Emil J. Tywoniak
85d2702ef6
opensta, sdc_expand: fix help
2025-11-19 15:20:50 +01:00
Emil J. Tywoniak
411fc149df
opensta: refactor default command
2025-11-19 15:20:50 +01:00
Emil J. Tywoniak
a5b6c3cc19
opensta, sdc_expand: more scratchpad
2025-11-19 15:20:50 +01:00
Emil J. Tywoniak
6846168db3
opensta: opensta.exe scratchpad variable
2025-11-19 15:20:50 +01:00
Emil J. Tywoniak
5acb77cab1
sdc_expand, opensta: typos
2025-11-19 15:20:50 +01:00
Emil J. Tywoniak
7bc88d5c40
sdc_expand: cleanup
2025-11-19 15:20:50 +01:00
Emil J. Tywoniak
793594bd59
sdc_expand: log header
2025-11-19 15:20:50 +01:00
Emil J. Tywoniak
7bed6ec658
opensta: quiet blackbox warning
2025-11-19 15:20:50 +01:00
Emil J. Tywoniak
0c4105d72c
opensta: quiet net width mismatch warning
2025-11-19 15:20:50 +01:00
Emil J. Tywoniak
bbf1e4bca2
sdc_expand, opensta: start
2025-11-19 15:20:50 +01:00
Akash Levy
a90a5e10d6
Merge branch 'YosysHQ:main' into main
2025-11-18 11:48:04 -05:00
Emil J. Tywoniak
f47540b950
techlibs: remove cells.lib
2025-11-14 15:40:14 +01:00
Akash Levy
55cd50f1a6
Merge branch 'YosysHQ:main' into main
2025-11-13 18:11:04 -05:00
Emil J. Tywoniak
f2263642a4
xilinx: fix IdString memory leak
2025-11-13 14:10:52 +01:00
Emil J. Tywoniak
a915143768
ice40: fix IdString memory leak
2025-11-13 14:10:52 +01:00
Emil J. Tywoniak
bc3fc21248
microchip: fix IdString memory leak
2025-11-13 14:10:52 +01:00
Akash Levy
11731c91f4
Merge from upstream
2025-11-04 22:20:34 -08:00
KrystalDelusion
39fab4a07f
Makefile: Add gatemate genfiles
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Allows files to be cleaned with `make clean`, without which it breaks out-of-tree builds if an in-tree build has previously run and subsequently cleaned.
2025-11-04 11:46:27 +13:00
Akash Levy
f620360782
Merge branch 'YosysHQ:main' into main
2025-10-29 17:36:24 -04:00
Akash Levy
6a07a6dfb4
Merge branch 'YosysHQ:main' into main
2025-10-29 04:52:50 -04:00
YRabbit
2a3720921c
Gowin. Fix GW5A ADCs.
...
For these primitives, Gowin decided to use a different option for
describing ports—directly in the module header, i.e.
``` verilog
module ADC(input CLK);
```
instead of
``` verilog
module ADC(CLK);
input CLK;
```
Since this one-time parser becomes too confusing, it is easier to simply
add ADC descriptions as they are from a separate file, especially since
these primitives are only available in the GW5A series.
Test:
``` shell
yosys -p "read_verilog top.v; synth_gowin -json top-synth.json -family gw5a"
```
The old version of Yosys simply won't compile the design due to the lack
of port descriptions, while the new version will compile without errors.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2025-10-29 12:48:21 +10:00
Patrick Urban
14c1802b01
gatemate: fix SERDES CDR parameters
2025-10-27 15:47:48 +01:00
Akash Levy
303f7292a0
Merge branch 'YosysHQ:main' into main
2025-10-25 20:30:52 -04:00
Mohamed Gaber
dec28f65ae
Merge remote-tracking branch 'donn/pyosys_bugfixes' into merge_pybind11
2025-10-26 02:39:43 +03:00
YRabbit
3956f103a9
Gowin. Handle the WRITE_MODE.
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Process the WRITE_MODE in the GW5A series in a more concise manner.
You can check it in the same way as in
https://github.com/YosysHQ/yosys/pull/5440
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2025-10-25 23:15:23 +01:00
YRabbit
64700dec65
Gowin. Disable unsupported BSRAM mode in GW5A
...
All supported (and planned to be supported) GW5A series chips do not
support the 2: Read-before-Write write mode.
Here, we prohibit the generation of BSRAM with this mode.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2025-10-23 09:59:56 +01:00
Maxim Kudinov
6535995005
synth_gowin: fix help hint style
2025-10-16 11:09:28 +01:00
Maxim Kudinov
8c347826f6
synth_gowin: make help description more clear
2025-10-16 11:09:28 +01:00
