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Merge branch 'YosysHQ:main' into main

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Akash Levy 2025-11-13 18:11:04 -05:00 • committed by GitHub
commit 55cd50f1a6
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10 changed files with 44 additions and 39 deletions
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4
techlibs/ice40/ice40_opt.cc
View file

@ -117,7 +117,7 @@ static void run_ice40_opts(Module *module)
if (GetSize(replacement_output)) {
optimized_co.insert(sigmap(cell->getPort(ID::CO)[0]));
auto it = cell->attributes.find(ID(SB_LUT4.name));
auto it = cell->attributes.find(IdString{"\\SB_LUT4.name"});
if (it != cell->attributes.end()) {
module->rename(cell, it->second.decode_string());
decltype(Cell::attributes) new_attr;
@ -126,7 +126,7 @@ static void run_ice40_opts(Module *module)
new_attr[a.first.c_str() + strlen("\\SB_LUT4.")] = a.second;
else if (a.first == ID::src)
new_attr.insert(std::make_pair(a.first, a.second));
else if (a.first.in(ID(SB_LUT4.name), ID::keep, ID::module_not_derived))
else if (a.first.in(IdString{"\\SB_LUT4.name"}, ID::keep, ID::module_not_derived))
continue;
else if (a.first.begins_with("\\SB_CARRY.\\"))
continue;

6
techlibs/ice40/ice40_wrapcarry.cc
View file

@ -62,7 +62,7 @@ void create_ice40_wrapcarry(ice40_wrapcarry_pm &pm)
cell->attributes[stringf("\\SB_CARRY.%s", a.first)] = a.second;
for (const auto &a : st.lut->attributes)
cell->attributes[stringf("\\SB_LUT4.%s", a.first)] = a.second;
cell->attributes[ID(SB_LUT4.name)] = Const(st.lut->name.str());
cell->attributes[IdString{"\\SB_LUT4.name"}] = Const(st.lut->name.str());
if (st.carry->get_bool_attribute(ID::keep) || st.lut->get_bool_attribute(ID::keep))
cell->attributes[ID::keep] = true;
@ -122,7 +122,7 @@ struct Ice40WrapCarryPass : public Pass {
carry->setPort(ID::CI, cell->getPort(ID::CI));
carry->setPort(ID::CO, cell->getPort(ID::CO));
module->swap_names(carry, cell);
auto lut_name = cell->attributes.at(ID(SB_LUT4.name), Const(NEW_ID.str())).decode_string();
auto lut_name = cell->attributes.at(IdString{"\\SB_LUT4.name"}, Const(NEW_ID.str())).decode_string();
auto lut = module->addCell(lut_name, ID($lut));
lut->setParam(ID::WIDTH, 4);
lut->setParam(ID::LUT, cell->getParam(ID::LUT));
@ -138,7 +138,7 @@ struct Ice40WrapCarryPass : public Pass {
lut->attributes[a.first.c_str() + strlen("\\SB_LUT4.")] = a.second;
else if (a.first == ID::src)
src = a.second;
else if (a.first.in(ID(SB_LUT4.name), ID::keep, ID::module_not_derived))
else if (a.first.in(IdString{"\\SB_LUT4.name"}, ID::keep, ID::module_not_derived))
continue;
else
continue;

2
techlibs/microchip/microchip_dsp.pmg
View file

@ -268,7 +268,7 @@ endmatch
code
if (postAdd)
{
if (postAdd->type.in(ID($sub)) && postAddAB == \A) {
if (postAdd->type.in($sub) && postAddAB == \A) {
// if $sub, the multiplier output must match to $sub.B, otherwise no match
} else {
u_postAddAB = postAddAB;

6
techlibs/microchip/microchip_dsp_cascade.pmg
View file

@ -115,9 +115,9 @@ finally
Wire *cascade = module->addWire(NEW_ID, 48);
// zero port C and move wire to cascade
dsp_pcin->setPort(ID(C), Const(0, 48));
dsp_pcin->setPort(ID(CDIN), cascade);
dsp->setPort(ID(CDOUT), cascade);
dsp_pcin->setPort(\C, Const(0, 48));
dsp_pcin->setPort(\CDIN, cascade);
dsp->setPort(\CDOUT, cascade);
// Configure wire to cascade the dsps
add_siguser(cascade, dsp_pcin);

28
techlibs/xilinx/xilinx_dsp_cascade.pmg
View file

@ -90,9 +90,9 @@ finally
if (i % MAX_DSP_CASCADE > 0) {
if (P >= 0) {
Wire *cascade = module->addWire(NEW_ID, 48);
dsp_pcin->setPort(ID(C), Const(0, 48));
dsp_pcin->setPort(ID(PCIN), cascade);
dsp->setPort(ID(PCOUT), cascade);
dsp_pcin->setPort(\C, Const(0, 48));
dsp_pcin->setPort(\PCIN, cascade);
dsp->setPort(\PCOUT, cascade);
add_siguser(cascade, dsp_pcin);
add_siguser(cascade, dsp);
@ -118,15 +118,15 @@ finally
}
if (AREG >= 0) {
Wire *cascade = module->addWire(NEW_ID, 30);
dsp_pcin->setPort(ID(A), Const(0, 30));
dsp_pcin->setPort(ID(ACIN), cascade);
dsp->setPort(ID(ACOUT), cascade);
dsp_pcin->setPort(\A, Const(0, 30));
dsp_pcin->setPort(\ACIN, cascade);
dsp->setPort(\ACOUT, cascade);
add_siguser(cascade, dsp_pcin);
add_siguser(cascade, dsp);
if (dsp->type.in(\DSP48E1))
dsp->setParam(ID(ACASCREG), AREG);
dsp_pcin->setParam(ID(A_INPUT), Const("CASCADE"));
dsp->setParam(\ACASCREG, AREG);
dsp_pcin->setParam(\A_INPUT, Const("CASCADE"));
log_debug("ACOUT -> ACIN cascade for %s -> %s\n", log_id(dsp), log_id(dsp_pcin));
}
@ -138,18 +138,18 @@ finally
// BCOUT from an adjacent DSP48A1 slice. The tools then
// translate BCOUT cascading to the dedicated BCIN input
// and set the B_INPUT attribute for implementation."
dsp_pcin->setPort(ID(B), cascade);
dsp_pcin->setPort(\B, cascade);
}
else {
dsp_pcin->setPort(ID(B), Const(0, 18));
dsp_pcin->setPort(ID(BCIN), cascade);
dsp_pcin->setPort(\B, Const(0, 18));
dsp_pcin->setPort(\BCIN, cascade);
}
dsp->setPort(ID(BCOUT), cascade);
dsp->setPort(\BCOUT, cascade);
add_siguser(cascade, dsp_pcin);
add_siguser(cascade, dsp);
if (dsp->type.in(\DSP48E1)) {
dsp->setParam(ID(BCASCREG), BREG);
dsp->setParam(\BCASCREG, BREG);
// According to UG389 p13 [https://www.xilinx.com/support/documentation/user_guides/ug389.pdf]
// "The attribute is only used by place and route tools and
// is not necessary for the users to set for synthesis. The
@ -158,7 +158,7 @@ finally
// BCOUT of another DSP48A1 slice, then the tools automatically
// set the attribute to 'CASCADE', otherwise it is set to
// 'DIRECT'".
dsp_pcin->setParam(ID(B_INPUT), Const("CASCADE"));
dsp_pcin->setParam(\B_INPUT, Const("CASCADE"));
}
log_debug("BCOUT -> BCIN cascade for %s -> %s\n", log_id(dsp), log_id(dsp_pcin));