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For these primitives, Gowin decided to use a different option for describing ports—directly in the module header, i.e. ``` verilog module ADC(input CLK); ``` instead of ``` verilog module ADC(CLK); input CLK; ``` Since this one-time parser becomes too confusing, it is easier to simply add ADC descriptions as they are from a separate file, especially since these primitives are only available in the GW5A series. Test: ``` shell yosys -p "read_verilog top.v; synth_gowin -json top-synth.json -family gw5a" ``` The old version of Yosys simply won't compile the design due to the lack of port descriptions, while the new version will compile without errors. Signed-off-by: YRabbit <rabbit@yrabbit.cyou> |
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| common | ||
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| easic | ||
| efinix | ||
| fabulous | ||
| gatemate | ||
| gowin | ||
| greenpak4 | ||
| ice40 | ||
| intel | ||
| intel_alm | ||
| lattice | ||
| microchip | ||
| nanoxplore | ||
| quicklogic | ||
| sf2 | ||
| xilinx | ||
| .gitignore | ||