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Merge branch 'YosysHQ:main' into main

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This commit is contained in:
Akash Levy 2026-02-04 15:53:43 -08:00 • committed by GitHub
commit d3ab45c2fa
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7 changed files with 11 additions and 4 deletions
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1
techlibs/common/prep.cc
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@ -211,6 +211,7 @@ struct PrepPass : public ScriptPass
run("memory_collect");
}
run(nokeepdc ? "opt -noff -fast" : "opt -noff -keepdc -fast");
run("sort");
}
if (check_label("check"))

1
techlibs/gowin/synth_gowin.cc
View file

@ -311,6 +311,7 @@ struct SynthGowinPass : public ScriptPass
if (check_label("map_luts"))
{
run("sort");
if (nowidelut && abc9) {
run("read_verilog -icells -lib -specify +/abc9_model.v");
run("abc9 -maxlut 4 -W 500");

2
techlibs/xilinx/synth_xilinx.cc
View file

@ -386,6 +386,8 @@ struct SynthXilinxPass : public ScriptPass
run("pmux2shiftx", "(skip if '-nosrl' and '-widemux=0')");
run("clean", " (skip if '-nosrl' and '-widemux=0')");
}
run("sort");
}
if (check_label("map_dsp", "(skip if '-nodsp')")) {