mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-02-21 15:57:36 +00:00
Code Activity

Move Design::sort() calls out of opt and opt_clean passes into the synth passes that need them.

Browse source
This commit is contained in:
Robert O'Callahan 2026-01-22 04:09:16 +00:00
parent 125609105d
commit e87bb65956
6 changed files with 5 additions and 3 deletions
Download patch file Download diff file Expand all files Collapse all files

1
techlibs/common/prep.cc
View file

@ -211,6 +211,7 @@ struct PrepPass : public ScriptPass
run("memory_collect");
}
run(nokeepdc ? "opt -noff -fast" : "opt -noff -keepdc -fast");
run("sort");
}
if (check_label("check"))

1
techlibs/gowin/synth_gowin.cc
View file

@ -311,6 +311,7 @@ struct SynthGowinPass : public ScriptPass
if (check_label("map_luts"))
{
run("sort");
if (nowidelut && abc9) {
run("read_verilog -icells -lib -specify +/abc9_model.v");
run("abc9 -maxlut 4 -W 500");

2
techlibs/xilinx/synth_xilinx.cc
View file

@ -386,6 +386,8 @@ struct SynthXilinxPass : public ScriptPass
run("pmux2shiftx", "(skip if '-nosrl' and '-widemux=0')");
run("clean", " (skip if '-nosrl' and '-widemux=0')");
}
run("sort");
}
if (check_label("map_dsp", "(skip if '-nodsp')")) {