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768 commits

Author SHA1 Message Date
Emil J. Tywoniak
9abee44602 opt_expr: replace invert_map with signorm traversal 2026-05-22 18:41:49 +02:00
Emil J. Tywoniak
6fd7f5c02d pmgen: hold sigmap pointer instead of owning it 2026-05-22 18:40:01 +02:00
Emil J. Tywoniak
5bfb631085 opt_expr: with -keepdc disable equality optimization rules that break when ports are sigmapped 2026-05-22 18:38:37 +02:00
Emil J. Tywoniak
aecc173f83 opt_dff: sigma harder, FfDataSigMapped 2026-05-22 18:38:37 +02:00
Emil J. Tywoniak
be7beaf91a opt_dff: temporarily disable signorm due to muxtree traversal 2026-05-22 18:38:37 +02:00
Emil J. Tywoniak
68bb5c6b94 signorm: disable in passes that use swap_names 2026-05-22 18:37:58 +02:00
Emil J. Tywoniak
4d2a6f2b7a opt_expr: fix invert_map 2026-05-22 18:37:58 +02:00
Emil J. Tywoniak
2f7d0913fc opt_hier: disable signorm 2026-05-22 18:37:58 +02:00
Emil J. Tywoniak
bb2d6f0e2a opt_merge_inc: re add initvals deletion 2026-05-22 18:37:13 +02:00
Emil J. Tywoniak
9d86a6636c wreduce: fixup initvals after setPort 2026-05-22 18:37:13 +02:00
Jannis Harder
423c8be71b WIP half broken snapshot 2026-05-22 18:37:11 +02:00
Emil J
e87a9bd9a7
Merge pull request #5888 from mikesinouye/pmux
opt_muxtree: reuse knowledge_t and pass by reference
2026-05-15 16:21:33 +00:00
Miodrag Milanović
36eceed720
Merge pull request #5862 from codexplorer-fish/cleaning-up-log-id
Cleaning up log_id()
2026-05-15 11:07:43 +00:00
Miodrag Milanovic
58df27ce7c Refactor uses of log_id in pgm files 2026-05-14 12:21:32 +02:00
Mike Inouye
e20a57b09e
Reuse knowledge_t and pass by reference 2026-05-13 10:57:18 -07:00
Emil J. Tywoniak
3a150f2883 remove unused hashlib containers 2026-05-12 12:52:10 +02:00
Codexplorer
e41b969da2 Refactored uses of log_id() 2026-05-08 20:59:24 -07:00
Emil J. Tywoniak
7fa660fc60 share: remove -force 2026-05-04 21:34:19 +02:00
Emil J. Tywoniak
e0b833ac1a opt_muxtree: dense knowledge 2026-04-24 11:07:58 +02:00
Emil J. Tywoniak
4abaca273e opt_reduce: further optimization 2026-04-24 11:07:58 +02:00
Emil J. Tywoniak
4f4672d17b muxpack: fix wide Y port handling 2026-03-19 00:12:49 +01:00
Emil J
c8f715fed8
Merge pull request #5664 from rocallahan/parallel-opt-clean
Parallelize `opt_clean` pass
2026-03-16 09:52:34 +00:00
Miodrag Milanovic
52533b0d1c Update opt_lut_ins and stat for analogdevices and remove ecp5 2026-03-06 09:10:36 +01:00
Robert O'Callahan
9c51ba1b09 Reduce opt_clean parallelism 2026-03-06 02:20:16 +00:00
Robert O'Callahan
8d8c05b338 Fix OptCleanPass usage of CleanRunContext to avoid constructing extra KeepCache and ParallelDispatchThreadPool 2026-03-06 02:20:16 +00:00
Robert O'Callahan
32f5044eaf Clarify "Not passing module as function argument" comment
This correct in terms of intent, it's just not fully enforced due to const laundering.
2026-03-06 02:20:16 +00:00
Emil J. Tywoniak
70cc2d67fd opt_clean: refactor 2026-03-06 02:20:14 +00:00
Robert O'Callahan
3603cd52a0 Pass the module Subpool to rmunused_module_signals and parallelize that function 2026-03-06 02:20:08 +00:00
Robert O'Callahan
19a7c8fcf3 Pass the module Subpool to rmunused_module_cells and parallelize that function 2026-03-06 02:20:08 +00:00
Robert O'Callahan
8e044d1045 Pass the module Subpool to rmunused_module_init and parallelize that function 2026-03-06 02:20:06 +00:00
Robert O'Callahan
a7437c636d Pass the toplevel thread pool to rmunused_module, create a Subpool, and parallelize remove_temporary_cells 2026-03-06 02:05:46 +00:00
Robert O'Callahan
887c32cb54 Create a toplevel ParallelDispatchThreadPool and parallelize keep_cache_t::scan_module() with it 2026-03-06 02:05:46 +00:00
Robert O'Callahan
72a21fe01d Introduce RmStats struct to encapsulate removal statistics
Turns out this is not strictly necessary for this PR but it's
still a good thing to do and makes it clearer that the stats
are not modified in a possibly racy way.
2026-03-06 02:05:43 +00:00
Robert O'Callahan
c2bb7d6a82 Make keep_cache_t process all modules up-front instead of on-demand
We will want to query `keep_cache` from parallel threads. If we compute
the results on-demand, that means we need synchronization for cache
access in those queries, which adds complexity and overhead. Instead, prefill
the cache with the status of all relevant modules. Note that this doesn't
actually do more work --- we always consult `keep_cache` for all cells of
all selected modules, so scanning all those cells and determining the kept
status of all dependency modules is always required.

Later in this PR we're going to parallelize `scan_module` itself, and that's also
much easier to do when no other parallel threads are running.
2026-03-06 02:05:04 +00:00
Emil J. Tywoniak
07ec8708e4 share: use newcelltypes 2026-03-04 12:22:14 +01:00
Emil J. Tywoniak
9e59f05c25 newcelltypes: wrap design celltypes support 2026-03-04 12:22:14 +01:00
Emil J. Tywoniak
35ccaa60d7 newcelltypes: TurboCellTypes -> StaticCellTypes 2026-03-04 12:22:14 +01:00
Emil J. Tywoniak
6adc08b0e5 opt_expr: use newcelltypes 2026-03-04 12:22:14 +01:00
Emil J. Tywoniak
3671d577a0 opt_clean: use newcelltypes 2026-03-04 12:22:14 +01:00
Emil J
1717fa0180
Merge pull request #5663 from YosysHQ/emil/opt_expr-fix-pow-shift
opt_expr: fix const lhs of $pow to $shl
2026-02-05 13:09:01 +01:00
Emil J
8bbde80e02
Merge pull request #5631 from rocallahan/cleanup-compare-signals
Clean up `compare_signals()` in `opt_clean`
2026-02-04 17:45:05 +01:00
Emil J
992e64342c
Merge pull request #5621 from rocallahan/remove-opt-sort
Remove `Design::sort()` calls from optimization passes
2026-02-04 16:55:56 +01:00
Emil J. Tywoniak
3bfeaee8ca opt_expr: fix const lhs of $pow to $shl 2026-02-03 11:59:00 +01:00
nella
8f6c4d40e4
Merge pull request #5623 from YosysHQ/nella/opt-dff-rewrite
opt_dff restructure.
2026-01-28 14:41:40 +01:00
nella
9367090763 OptDff more accurate ctrl/pattern desc. 2026-01-26 22:19:36 +01:00
nella
5803461c24 opt_dff pattern extraction. 2026-01-26 22:10:10 +01:00
nella
8576055dea Fix tests. 2026-01-26 18:41:41 +01:00
nella
a75e0b2e92 opt_dff minor cleanup, added tests for comp var. 2026-01-26 14:24:01 +01:00
Robert O'Callahan
32e96605d4 Don't update used_signals for retained wires in rmunused_module_signals.
These updates should not be necessary. In fact, if they were necessary, this code
would be buggy, because the results would depend on the order in which wires are traversed:
If wire A is retained, which causes an update to `used_signals`, which then causes wire B
to be retained when it otherwise wouldn't be, then we would get different results depending
on whether A is visited before B.

These updates will also make it difficult to process these wires in parallel.
2026-01-24 03:41:18 +00:00
Robert O'Callahan
7d53d64a47 Make the call to compare_signals() easier to read.
The negation here is confusing. The intent of the code is "if `s1` is preferred
over `s2` as the canonical `SigBit` for this signal, make `s1` the canonical `SigBit`
in `assign_map`", so write the code that way instead of "if `s2` is not preferred
over `s1` ...".

This doesn't change any behavior now that `compare_signals()` is a total order,
i.e. `s1` is preferred over `s2`, `s2` is preferred over `s1`, or `s1` and `s2` are equal.
Now, when `s1` and `s2` are equal, we don't call `assign_map.add(s1)`, but that's
already a noop in that case.
2026-01-24 02:01:05 +00:00