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remove unused hashlib containers

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This commit is contained in:
Emil J. Tywoniak 2026-05-12 12:52:10 +02:00
parent 4eb1c61bd5
commit 3a150f2883
6 changed files with 4 additions and 8 deletions
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1
passes/equiv/equiv_make.cc
View file

@ -79,6 +79,7 @@ struct EquivMakeWorker
if (token == ".fsm") {
IdString modname = RTLIL::escape_id(next_token(line));
(void)modname;
IdString signame = RTLIL::escape_id(next_token(line));
if (encdata.count(signame))
log_cmd_error("Re-definition of signal '%s' in encfile '%s'!\n", signame, fn);

1
passes/opt/muxpack.cc
View file

@ -263,7 +263,6 @@ struct MuxpackWorker
int cases = GetSize(chain) - cursor;
Cell *first_cell = chain[cursor];
dict<int, SigBit> taps_dict;
if (cases < 2) {
cursor++;

4
passes/opt/opt_lut.cc
View file

@ -421,13 +421,12 @@ struct OptLutWorker
}
RTLIL::Cell *lutM, *lutR;
pool<SigBit> lutM_inputs, lutR_inputs;
pool<SigBit> lutR_inputs;
pool<int> lutM_dlogic_inputs;
if (combine == COMBINE_A)
{
log_debug(" Combining LUTs into cell A.\n");
lutM = lutA;
lutM_inputs = lutA_inputs;
lutM_dlogic_inputs = lutA_dlogic_inputs;
lutR = lutB;
lutR_inputs = lutB_inputs;
@ -436,7 +435,6 @@ struct OptLutWorker
{
log_debug(" Combining LUTs into cell B.\n");
lutM = lutB;
lutM_inputs = lutB_inputs;
lutM_dlogic_inputs = lutB_dlogic_inputs;
lutR = lutA;
lutR_inputs = lutA_inputs;

1
passes/sat/qbfsat.h
View file

@ -170,7 +170,6 @@ struct QbfSolutionType {
std::smatch m;
bool sat_regex_found = false;
bool unsat_regex_found = false;
dict<std::string, bool> hole_value_recovered;
for (const std::string &x : stdout_lines) {
if(std::regex_search(x, m, hole_value_regex)) {
std::string loc = m[1].str();

1
passes/techmap/abc9_ops.cc
View file

@ -97,7 +97,6 @@ void check(RTLIL::Design *design, bool dff_mode)
ID($_DLATCHSR_PNN_), ID($_DLATCHSR_PNP_), ID($_DLATCHSR_PPN_), ID($_DLATCHSR_PPP_),
ID($_SR_NN_), ID($_SR_NP_), ID($_SR_PN_), ID($_SR_PP_)
};
pool<IdString> processed;
for (auto module : design->selected_modules())
for (auto cell : module->cells()) {
auto inst_module = design->module(cell->type);

4
passes/techmap/flowmap.cc
View file

@ -1246,14 +1246,14 @@ struct FlowmapWorker
}
}
log(" Breaking LUT %s to %s LUT %s (potential %d).\n",
log_signal(breaking_lut), lut_nodes[breaking_gate] ? "reuse" : "extract", log_signal(breaking_gate), best_potential);
log_signal(breaking_lut), lut_nodes[breaking_gate] ? "reuse" : "extract", log_signal(breaking_gate), best_potential);
if (debug_relax)
log(" Removing breaking gate %s from LUT.\n", log_signal(breaking_gate));
lut_gates[breaking_lut].erase(breaking_gate);
auto cut_inputs = cut_lut_at_gate(breaking_lut, breaking_gate);
pool<RTLIL::SigBit> gate_inputs = cut_inputs.first, other_inputs = cut_inputs.second;
pool<RTLIL::SigBit> gate_inputs = cut_inputs.first;
pool<RTLIL::SigBit> worklist = lut_gates[breaking_lut];
pool<RTLIL::SigBit> elim_gates = gate_inputs;