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Refactor uses of log_id in pgm files

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This commit is contained in:
Miodrag Milanovic 2026-05-14 12:21:32 +02:00
parent c6f53aec5f
commit 58df27ce7c
8 changed files with 12 additions and 12 deletions
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2
passes/opt/peepopt_formal_clockgateff.pmg
View file

@ -44,7 +44,7 @@ endmatch
code
log("replacing clock gate pattern in %s with ff: latch=%s, and=%s\n",
log_id(module), log_id(latch), log_id(and_gate));
module, latch, and_gate);
// Add a flip-flop and rewire the AND gate to use the output of this flop
// instead of the latch. We don't delete the latch in case its output is

2
passes/opt/peepopt_muldiv.pmg
View file

@ -32,7 +32,7 @@ code
val_y.extend_u0(GetSize(div_y), param(div, \A_SIGNED).as_bool());
did_something = true;
log("muldiv pattern in %s: mul=%s, div=%s\n", log_id(module), log_id(mul), log_id(div));
log("muldiv pattern in %s: mul=%s, div=%s\n", module, mul, div);
module->connect(div_y, val_y);
autoremove(div);
accept;

2
passes/opt/peepopt_muldiv_c.pmg
View file

@ -119,7 +119,7 @@ code
autoremove(div);
// Log, fixup, accept
log("muldiv_const pattern in %s: mul=%s, div=%s\n", log_id(module), log_id(mul), log_id(div));
log("muldiv_const pattern in %s: mul=%s, div=%s\n", module, mul, div);
mul->fixup_parameters();
accept;
endcode

2
passes/opt/peepopt_shiftadd.pmg
View file

@ -112,7 +112,7 @@ code
did_something = true;
log("shiftadd pattern in %s: shift=%s, add/sub=%s, offset: %d\n", \
log_id(module), log_id(shift), log_id(add), offset);
module, shift, add, offset);
SigSpec new_a;
if(offset<0) {

2
passes/opt/peepopt_shiftmul_left.pmg
View file

@ -99,7 +99,7 @@ code
}
did_something = true;
log("left shiftmul pattern in %s: shift=%s, mul=%s\n", log_id(module), log_id(shift), log_id(mul));
log("left shiftmul pattern in %s: shift=%s, mul=%s\n", module, shift, mul);
int const_factor = mul_const.as_int();
int new_const_factor = 1 << factor_bits;

2
passes/opt/peepopt_shiftmul_right.pmg
View file

@ -76,7 +76,7 @@ code
reject;
did_something = true;
log("right shiftmul pattern in %s: shift=%s, mul=%s\n", log_id(module), log_id(shift), log_id(mul));
log("right shiftmul pattern in %s: shift=%s, mul=%s\n", module, shift, mul);
int const_factor = mul_const.as_int();
int new_const_factor = 1 << factor_bits;

4
techlibs/microchip/microchip_dsp_cascade.pmg
View file

@ -135,10 +135,10 @@ finally
}
log_debug("PCOUT -> PCIN cascade for %s -> %s\n", log_id(dsp), log_id(dsp_pcin));
log_debug("PCOUT -> PCIN cascade for %s -> %s\n", dsp, dsp_pcin);
} else {
log_debug(" Blocking %s -> %s cascade (exceeds max: %d)\n", log_id(dsp), log_id(dsp_pcin), MAX_DSP_CASCADE);
log_debug(" Blocking %s -> %s cascade (exceeds max: %d)\n", dsp, dsp_pcin, MAX_DSP_CASCADE);
}
dsp = dsp_pcin;

8
techlibs/xilinx/xilinx_dsp_cascade.pmg
View file

@ -114,7 +114,7 @@ finally
}
dsp_pcin->setPort(\OPMODE, opmode);
log_debug("PCOUT -> PCIN cascade for %s -> %s\n", log_id(dsp), log_id(dsp_pcin));
log_debug("PCOUT -> PCIN cascade for %s -> %s\n", dsp, dsp_pcin);
}
if (AREG >= 0) {
Wire *cascade = module->addWire(NEW_ID, 30);
@ -128,7 +128,7 @@ finally
dsp->setParam(\ACASCREG, AREG);
dsp_pcin->setParam(\A_INPUT, Const("CASCADE"));
log_debug("ACOUT -> ACIN cascade for %s -> %s\n", log_id(dsp), log_id(dsp_pcin));
log_debug("ACOUT -> ACIN cascade for %s -> %s\n", dsp, dsp_pcin);
}
if (BREG >= 0) {
Wire *cascade = module->addWire(NEW_ID, 18);
@ -161,11 +161,11 @@ finally
dsp_pcin->setParam(\B_INPUT, Const("CASCADE"));
}
log_debug("BCOUT -> BCIN cascade for %s -> %s\n", log_id(dsp), log_id(dsp_pcin));
log_debug("BCOUT -> BCIN cascade for %s -> %s\n", dsp, dsp_pcin);
}
}
else {
log_debug(" Blocking %s -> %s cascade (exceeds max: %d)\n", log_id(dsp), log_id(dsp_pcin), MAX_DSP_CASCADE);
log_debug(" Blocking %s -> %s cascade (exceeds max: %d)\n", dsp, dsp_pcin, MAX_DSP_CASCADE);
}
dsp = dsp_pcin;