456 commits

Author	SHA1	Message	Date
Akash Levy	70016a08b8	Disable debug	2024-07-03 06:55:53 -07:00
Akash Levy	30241e07eb	Fix segfault	2024-07-03 02:29:48 -07:00
Akash Levy	fcd073ab51	Smallfix	2024-07-02 15:13:58 -07:00
Akash Levy	0596766cbd	Merge upstream yosys changes	2024-07-01 18:33:38 -07:00
Akash Levy	dec43679be	See if this fixes issues on Innatera design	2024-06-28 03:13:38 -07:00
Akash Levy	719bbd7523	Improve SCC reporting	2024-06-17 14:18:41 -07:00
Miodrag Milanovic	dfde792288	Refactored import code	2024-06-17 14:49:58 +02:00
Miodrag Milanovic	19da7f7d59	Update makefile to make options uniform	2024-06-17 13:29:11 +02:00
Miodrag Milanovic	0f3f731254	Handle -work for vhdl, and clean messages	2024-06-17 13:29:11 +02:00
Miodrag Milanovic	0a81c8e161	Import all modules from all libraries when when needed	2024-06-17 13:29:11 +02:00
Miodrag Milanovic	7c3094633d	Compile with hier_tree separate SV and VHDL as well	2024-06-17 13:29:11 +02:00
Miodrag Milanovic	e2e189647f	Cleanup	2024-06-17 13:29:11 +02:00
Miodrag Milanovic	7bec332b68	SV + VHDL with RTL support	2024-06-17 13:29:11 +02:00
Miodrag Milanovic	25d50bb2af	VHDL only build support	2024-06-17 13:29:11 +02:00
Miodrag Milanovic	54bf9ccf06	Add initial support for Verific without additional YosysHQ patch	2024-06-17 13:29:11 +02:00
Akash Levy	a0c0384683	Preserve instances	2024-06-16 20:20:10 -07:00
Akash Levy	e23e33441f	Update yosys from upstream	2024-06-15 14:23:24 -07:00
Akash Levy	fce46d2a53	Add better Yosys/Verific name aliasing and reenable dffe opt	2024-06-15 14:18:33 -07:00
Akash Levy	2337d97977	Sub1 fix	2024-06-13 15:33:17 -07:00
Akash Levy	ac0a9e7366	Updates	2024-06-10 20:52:11 -07:00
Akash Levy	b9b776d211	Update for no preservation of user nets	2024-06-10 20:33:05 -07:00
Akash Levy	d930310599	Enable more updates	2024-06-09 13:54:34 -07:00
Mike Inouye	b0ab1cf8c3	Fix memory leak in verific file parsing. ... Signed-off-by: Mike Inouye <mikeinouye@google.com>	2024-06-07 22:51:28 +00:00
Akash Levy	8499d31cf2	Revert veri_break_loops setting	2024-06-07 00:09:01 -07:00
Akash Levy	c8f7441a4a	Fix skip default value	2024-06-05 09:33:03 -07:00
Akash Levy	c59a997255	Ignore files properly	2024-06-05 07:53:21 -07:00
Akash Levy	4d44099d09	Support for ignoring translate_off and ignoring files	2024-06-05 05:00:05 -07:00
Akash Levy	5dc62bec0b	Support .inc files and readmemh missing file	2024-06-03 20:05:30 -07:00
Akash Levy	92e44cc9a3	Minor fix to ignore files	2024-06-03 18:17:50 -07:00
Akash Levy	4339b3681a	Elaborate top level modules undo	2024-06-03 16:17:51 -07:00
Akash Levy	a692bf17d7	Improper ignore translates	2024-06-03 11:23:16 -07:00
Akash Levy	783c0a593a	Actually optimize with Verific now	2024-06-03 04:55:47 -07:00
Akash Levy	4475b50ffa	Undo some ugly stuff and make more attempted fixes	2024-06-02 23:33:23 -07:00
Akash Levy	2585636d18	Use ability to get/set IMPORT runtime flags	2024-06-02 22:24:29 -07:00
Akash Levy	28a03380b7	Priority selector fixes (opt order), relaxed checking, warning if using Yosys case statements	2024-06-02 18:45:31 -07:00
Akash Levy	85cbd05bb1	Update some runtime flags to fix some potential issues	2024-06-02 01:12:43 -07:00
Akash Levy	5bc23b272a	Add blackboxes a little later and use ignore files rather than ignore modules	2024-05-30 14:17:10 -07:00
Akash Levy	a55a4d461e	Infer wide operators pre elaboration (post does not work as well!)	2024-05-28 04:39:29 -07:00
Akash Levy	4062825a9e	Disable Liberty support, add blackbox Verilog module, and add attribute parsing into Yosys Liberty parser	2024-05-28 01:47:46 -07:00
Akash Levy	b90c20cd14	Update Verific, add opt to hierarchy pass, make opt run a bunch of Verific optimizations, update some Verific runtime flags	2024-05-27 21:56:08 -07:00
Akash Levy	a98fcbd48b	Revert Verific flags	2024-05-25 23:21:31 -07:00
Akash Levy	60ce37c2bd	Don't reenable verific, move to c_cpp_properties.json in .vscode	2024-05-24 01:49:54 -07:00
Akash Levy	22bdf4035a	Verific to handle all RAMs	2024-05-24 01:08:37 -07:00
Akash Levy	6300c491ea	Update Yosys runtime flags for Verific to remove multi-port memory support	2024-05-24 00:26:37 -07:00
Akash Levy	66eabb1d2c	Define SYNTH and OVL_SVA by default	2024-05-23 21:05:57 -07:00
Akash Levy	187737b86a	Don't adjust naming on imported cells. Add $ for each pass	2024-05-19 15:02:40 -07:00
Akash Levy	60e598b9c8	Define SYNTHESIS earlier and in both, support ignored module specification	2024-05-17 04:46:28 -07:00
Akash Levy	375f73bbce	Update for Amba support	2024-05-15 15:37:14 -07:00
Akash Levy	ed42470d45	Move ignore translate up here and update verificc	2024-05-14 16:02:33 -07:00
Akash Levy	81b542fd31	Updated to support Amba comments and .h files	2024-05-14 13:25:43 -07:00