Emil J. Tywoniak
6f2053fc90
verilog_lexer: refactor
2025-08-08 13:03:02 +02:00
Emil J. Tywoniak
50c5956187
ast: refactor
2025-08-08 13:03:02 +02:00
Emil J. Tywoniak
32792815eb
ast: remove null_check as dead code
2025-08-08 12:32:43 +02:00
Emil J. Tywoniak
5e8986be4f
simplify: simplify
2025-08-08 12:31:40 +02:00
Emil J. Tywoniak
4f77113960
simplify: std::gcd
2025-08-08 12:31:13 +02:00
Krystine Sherwin
c634a4c926
simplify.cc: Drop unused debug prints
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At least the ones added by this PR. There are some unused debug prints that are *changed* by this PR, but I've left them.
2025-08-08 17:14:31 +12:00
Krystine Sherwin
5be7a91149
frontends/ast: More usage of auto
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For consistency.
2025-08-08 17:10:16 +12:00
Emil J. Tywoniak
7047bc26b3
preproc: formatting
2025-07-19 22:57:53 +02:00
Emil J. Tywoniak
e77252ce8d
verilog_lexer, verilog_parser: remove comment
2025-07-19 22:56:48 +02:00
Emil J. Tywoniak
6b59d05282
verilog_lexer: fix fallthrough warning
2025-07-19 22:53:02 +02:00
Emil J
588c5d5a57
verilog_lexer: remove comment
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Co-authored-by: KrystalDelusion <93062060+KrystalDelusion@users.noreply.github.com>
2025-07-19 22:46:17 +02:00
Emil J. Tywoniak
66a9fc9fe0
preproc: formatting
2025-07-19 22:45:19 +02:00
Emil J. Tywoniak
ca24169659
verilog: fix build dependency graph
2025-07-10 23:59:54 +02:00
Gary Wong
e17ed5df88
verilog: add support for SystemVerilog string literals.
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Differences are new escape sequences (including escaped newline
continuations and hex escapes) and triple-quoted literals.
2025-07-10 23:28:22 +02:00
garytwong
a519390fc4
verilog: fix string literal regular expression ( #5187 )
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* verilog: fix string literal regular expression.
A backslash was improperly quoted, causing string literal matching
to fail when the final token before a closing quote was an escaped
backslash.
* verilog: add regression test for string literal regex bug.
Test for bug triggered by escaped backslash immediately before
closing quote (introduced in ca7d94af40aa7eaf
2025-07-10 23:16:50 +02:00
Emil J. Tywoniak
56058b3ed4
read_verilog, ast: use unified locations in errors and simplify dependencies
2025-07-10 21:15:50 +02:00
Emil J. Tywoniak
41d9a1b88e
readme, verilog_parser: bison 3.8 and ubuntu 22.04 example
2025-07-10 21:15:50 +02:00
Krystine Sherwin
7e026d824a
dpicall.cc: Fix sans-plugin function call
2025-07-10 21:15:50 +02:00
Krystine Sherwin
a2b2188a7f
preproc.cc: Use full path for generated file
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Fixes out-of-tree builds.
2025-07-10 21:15:50 +02:00
Krystine Sherwin
7b5035e0c4
preproc depends on parser
2025-07-10 21:15:50 +02:00
Emil J. Tywoniak
040d717ad7
fixup! fixup! ast, read_verilog: unify location types, reduce filename copying
2025-07-10 21:15:50 +02:00
Emil J. Tywoniak
ed0582c9f2
fixup! ast, read_verilog: unify location types, reduce filename copying
2025-07-10 21:15:50 +02:00
Emil J. Tywoniak
81e5270484
ast, read_verilog: unify location types, reduce filename copying
2025-07-10 21:15:50 +02:00
Emil J. Tywoniak
b276fb6616
neater errors, lost in the sauce of source
2025-07-10 21:15:50 +02:00
Emil J. Tywoniak
88800a16ea
ast, read_verilog: refactoring
2025-07-10 21:15:50 +02:00
Emil J. Tywoniak
31002cf259
ast: fix new memory safety bugs from rebase
2025-07-10 21:15:50 +02:00
Emil J. Tywoniak
6cb789b2c2
ast: ownership for string values
2025-07-10 21:15:50 +02:00
Emil J. Tywoniak
8a873a7724
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-07-10 21:15:50 +02:00
Emil J. Tywoniak
bb08919105
Revert "verilog: fix string literal regular expression ( #5187 )"
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This reverts commit 834a7294b7
2025-07-10 21:15:38 +02:00
Emil J. Tywoniak
dc204dc909
Revert "verilog: add support for SystemVerilog string literals."
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This reverts commit 5feb1a1752
2025-07-10 21:14:38 +02:00
Emil J. Tywoniak
e0822c048e
Revert "verilog: fix parser "if" memory errors."
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This reverts commit 34a2abeddb
2025-07-10 21:13:28 +02:00
N. Engelhardt
e47f5369fd
verificsva: check -L value is small enough for code to work
2025-07-09 15:58:35 +02:00
KrystalDelusion
1a215719e5
Merge pull request #5192 from garytwong/multiline-string
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verilog: support newline and hex escapes in string literals
2025-07-08 10:27:01 +12:00
N. Engelhardt
642756a9c6
Merge pull request #5178 from jix/sva_cover_only_followed_by
2025-07-07 10:07:06 +02:00
Gary Wong
5feb1a1752
verilog: add support for SystemVerilog string literals.
...
Differences are new escape sequences (including escaped newline
continuations and hex escapes) and triple-quoted literals.
2025-07-03 20:51:12 -06:00
Miodrag Milanovic
eed3bc243f
verific: enable replacing const exprs in static elaboration by default
2025-07-02 11:54:19 +02:00
N. Engelhardt
7b0c1fe491
Merge pull request #5102 from YosysHQ/krys/verilog_no_select
2025-06-30 13:35:17 +00:00
Gary Wong
34a2abeddb
verilog: fix parser "if" memory errors.
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Fix buggy memory allocation introduced in #5152 :
1) clean up ast_stack to reflect AST node rearrangement when necessary,
to avoid dangling pointer;
2) call free_attr() on unused attribute list when no new syntax node is
created, to avoid leaking it.
2025-06-22 23:57:42 -04:00
garytwong
834a7294b7
verilog: fix string literal regular expression ( #5187 )
...
* verilog: fix string literal regular expression.
A backslash was improperly quoted, causing string literal matching
to fail when the final token before a closing quote was an escaped
backslash.
* verilog: add regression test for string literal regex bug.
Test for bug triggered by escaped backslash immediately before
closing quote (introduced in ca7d94af40aa7eaf
2025-06-19 12:41:18 -04:00
Jannis Harder
f019e44e74
verificsva: Support the followed-by operator in cover mode
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The implementation for the implication operator in cover mode actually
implements the followed-by operator, so we can re-use it unchanged.
It is not always the correct behavior for the implication operator in
cover mode, but a) it will only cause false positives not miss anything
so if the behavior is unexpected it will be visible in the produced
traces, b) it is unlikely to make a difference for most properties one
would practically use in cover mode, c) at least one other widely used
SVA implementations behaves the same way and d) it's not clear whether
we can fix this without rewriting most of verificsva.cc
2025-06-13 21:27:31 +02:00
KrystalDelusion
67f8de54dc
Merge pull request #5160 from garytwong/fast-lex
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verilog: improve string literal matching speed (fixes #5076 )
2025-06-13 09:57:01 +12:00
KrystalDelusion
82888580ac
Merge pull request #5152 from garytwong/unique-if
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verilog: implement SystemVerilog unique/unique0/priority if semantics.
2025-06-13 09:56:53 +12:00
N. Engelhardt
f22248f056
downgrade verific warnings about common coding styles
2025-06-06 16:30:50 +02:00
Emil J
378add3723
Merge pull request #5163 from YosysHQ/emil/fix-single-bit-vector-leak
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simplify: fix single_bit_vector memory leak
2025-06-04 17:00:54 +02:00
George Rennie
0fcf5c080d
Merge pull request #5158 from georgerennie/george/task_inout
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read_verilog/astsimplify: copy inout ports in and out of functions/tasks
2025-06-04 14:23:08 +01:00
George Rennie
ab40403d90
Merge pull request #5154 from georgerennie/george/post_incdec_undo_fix
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read_verilog: fix -1 constant used to correct post increment/decrement
2025-06-04 14:22:32 +01:00
Emil J. Tywoniak
c37b7b3bf4
simplify: fix single_bit_vector memory leak
2025-06-04 10:32:03 +02:00
Gary Wong
ca7d94af99
verilog: improve string literal matching speed ( fixes #5076 )
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Use a greedy regular expression to match input inside a string
literal, so that flex can accumulate a longer match instead of
invoking a rule for each individual character.
2025-05-31 22:38:44 -06:00
George Rennie
45e8ff476e
read_verilog: copy inout ports in and out of functions/tasks
2025-05-31 01:09:03 +01:00
KrystalDelusion
545753cc5a
Merge pull request #5143 from YosysHQ/krys/typedef_struct_global
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SystemVerilog: Fix typedef struct in global space
2025-05-31 09:59:26 +12:00
