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ast, read_verilog: unify location types, reduce filename copying
This commit is contained in:
Emil J. Tywoniak
parent
b276fb6616
commit
81e5270484
12 changed files with 715 additions and 693 deletions
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@ -207,7 +207,7 @@ AstNode::AstNode(AstSrcLocType loc, AstNodeType type, std::unique_ptr<AstNode> c
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astnodes++;
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this->type = type;
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loc = loc;
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location = loc;
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is_input = false;
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is_output = false;
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is_reg = false;
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@ -921,7 +921,7 @@ std::unique_ptr<AstNode> AstNode::mktemp_logic(AstSrcLocType loc, const std::str
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{
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auto wire_owned = std::make_unique<AstNode>(loc, AST_WIRE, std::make_unique<AstNode>(loc, AST_RANGE, mkconst_int(loc, range_left, true), mkconst_int(loc, range_right, true)));
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auto* wire = wire_owned.get();
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wire->str = stringf("%s%s:%d$%d", name.c_str(), RTLIL::encode_filename(location.filename).c_str(), location.first_line, autoidx++);
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wire->str = stringf("%s%s:%d$%d", name.c_str(), RTLIL::encode_filename(*location.begin.filename).c_str(), location.begin.line, autoidx++);
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if (nosync)
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wire->set_attribute(ID::nosync, AstNode::mkconst_int(loc, 1, false));
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wire->is_signed = is_signed;
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@ -1085,7 +1085,7 @@ RTLIL::Const AstNode::realAsConst(int width)
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std::string AstNode::loc_string() const
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{
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return stringf("%s:%d.%d-%d.%d", location.filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
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return stringf("%s:%d.%d-%d.%d", location.begin.filename->c_str(), location.begin.line, location.begin.column, location.end.line, location.end.column);
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}
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void AST::set_src_attr(RTLIL::AttrObject *obj, const AstNode *ast)
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@ -1246,7 +1246,7 @@ static RTLIL::Module *process_module(RTLIL::Design *design, AstNode *ast, bool d
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ast->children.swap(new_children);
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if (ast->attributes.count(ID::blackbox) == 0) {
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ast->set_attribute(ID::blackbox, AstNode::mkconst_int(1, false));
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ast->set_attribute(ID::blackbox, AstNode::mkconst_int(ast->location, 1, false));
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}
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}
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@ -1443,7 +1443,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool nodisplay, bool dump
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if (design->has(child->str)) {
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RTLIL::Module *existing_mod = design->module(child->str);
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if (!nooverwrite && !overwrite && !existing_mod->get_blackbox_attribute()) {
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log_file_error(child->location.filename, child->location.first_line, "Re-definition of module `%s'!\n", child->str.c_str());
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log_file_error(*child->location.begin.filename, child->location.begin.line, "Re-definition of module `%s'!\n", child->str.c_str());
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} else if (nooverwrite) {
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log("Ignoring re-definition of module `%s' at %s.\n",
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child->str.c_str(), child->loc_string().c_str());
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@ -1526,7 +1526,8 @@ AstNode * AST::find_modport(AstNode *intf, std::string name)
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void AST::explode_interface_port(AstNode *module_ast, RTLIL::Module * intfmodule, std::string intfname, AstNode *modport)
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{
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for (auto w : intfmodule->wires()){
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auto wire = std::make_unique<AstNode>(AST_WIRE, std::make_unique<AstNode>(AST_RANGE, AstNode::mkconst_int(w->width -1, true), AstNode::mkconst_int(0, true)));
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auto loc = module_ast->location;
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auto wire = std::make_unique<AstNode>(loc, AST_WIRE, std::make_unique<AstNode>(loc, AST_RANGE, AstNode::mkconst_int(loc, w->width -1, true), AstNode::mkconst_int(loc, 0, true)));
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std::string origname = log_id(w->name);
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std::string newname = intfname + "." + origname;
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wire->str = newname;
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@ -1583,11 +1584,12 @@ void AstModule::expand_interfaces(RTLIL::Design *design, const dict<RTLIL::IdStr
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loadconfig();
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auto new_ast = ast->clone();
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auto loc = ast->location;
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for (auto &intf : local_interfaces) {
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std::string intfname = intf.first.str();
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RTLIL::Module *intfmodule = intf.second;
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for (auto w : intfmodule->wires()){
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auto wire = std::make_unique<AstNode>(AST_WIRE, std::make_unique<AstNode>(AST_RANGE, AstNode::mkconst_int(w->width -1, true), AstNode::mkconst_int(0, true)));
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auto wire = std::make_unique<AstNode>(loc, AST_WIRE, std::make_unique<AstNode>(loc, AST_RANGE, AstNode::mkconst_int(loc, w->width -1, true), AstNode::mkconst_int(loc, 0, true)));
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std::string newname = log_id(w->name);
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newname = intfname + "." + newname;
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wire->str = newname;
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@ -1615,9 +1617,9 @@ void AstModule::expand_interfaces(RTLIL::Design *design, const dict<RTLIL::IdStr
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if (design->module(interface_type) != nullptr) {
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// Add a cell to the module corresponding to the interface port such that
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// it can further propagated down if needed:
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auto celltype_for_intf = std::make_unique<AstNode>(AST_CELLTYPE);
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auto celltype_for_intf = std::make_unique<AstNode>(loc, AST_CELLTYPE);
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celltype_for_intf->str = interface_type;
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auto cell_for_intf = std::make_unique<AstNode>(AST_CELL, std::move(celltype_for_intf));
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auto cell_for_intf = std::make_unique<AstNode>(loc, AST_CELL, std::move(celltype_for_intf));
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cell_for_intf->str = name_port + "_inst_from_top_dummy";
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new_ast->children.push_back(std::move(cell_for_intf));
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@ -1824,8 +1826,9 @@ std::string AstModule::derive_common(RTLIL::Design *design, const dict<RTLIL::Id
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rewritten.reserve(GetSize(parameters));
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auto new_ast = ast->clone();
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auto loc = ast->location;
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if (!new_ast->attributes.count(ID::hdlname))
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new_ast->set_attribute(ID::hdlname, AstNode::mkconst_str(stripped_name.substr(1)));
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new_ast->set_attribute(ID::hdlname, AstNode::mkconst_str(loc, stripped_name.substr(1)));
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para_counter = 0;
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for (auto& child : new_ast->children) {
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@ -1849,12 +1852,12 @@ std::string AstModule::derive_common(RTLIL::Design *design, const dict<RTLIL::Id
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if (param_has_no_default(child))
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child->children.insert(child->children.begin(), nullptr);
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if ((it->second.flags & RTLIL::CONST_FLAG_REAL) != 0) {
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child->children[0] = std::make_unique<AstNode>(AST_REALVALUE);
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child->children[0] = std::make_unique<AstNode>(loc, AST_REALVALUE);
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child->children[0]->realvalue = std::stod(it->second.decode_string());
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} else if ((it->second.flags & RTLIL::CONST_FLAG_STRING) != 0)
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child->children[0] = AstNode::mkconst_str(it->second.decode_string());
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child->children[0] = AstNode::mkconst_str(loc, it->second.decode_string());
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else
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child->children[0] = AstNode::mkconst_bits(it->second.to_bits(), (it->second.flags & RTLIL::CONST_FLAG_SIGNED) != 0);
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child->children[0] = AstNode::mkconst_bits(loc, it->second.to_bits(), (it->second.flags & RTLIL::CONST_FLAG_SIGNED) != 0);
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rewritten.insert(it->first);
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}
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@ -1862,12 +1865,12 @@ std::string AstModule::derive_common(RTLIL::Design *design, const dict<RTLIL::Id
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for (const auto ¶m : parameters) {
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if (rewritten.count(param.first))
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continue;
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auto defparam = std::make_unique<AstNode>(AST_DEFPARAM, std::make_unique<AstNode>(AST_IDENTIFIER));
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auto defparam = std::make_unique<AstNode>(loc, AST_DEFPARAM, std::make_unique<AstNode>(loc, AST_IDENTIFIER));
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defparam->children[0]->str = param.first.str();
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if ((param.second.flags & RTLIL::CONST_FLAG_STRING) != 0)
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defparam->children.push_back(AstNode::mkconst_str(param.second.decode_string()));
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defparam->children.push_back(AstNode::mkconst_str(loc, param.second.decode_string()));
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else
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defparam->children.push_back(AstNode::mkconst_bits(param.second.to_bits(), (param.second.flags & RTLIL::CONST_FLAG_SIGNED) != 0));
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defparam->children.push_back(AstNode::mkconst_bits(loc, param.second.to_bits(), (param.second.flags & RTLIL::CONST_FLAG_SIGNED) != 0));
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new_ast->children.push_back(std::move(defparam));
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}
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@ -1922,7 +1925,7 @@ void AstNode::input_error(const char *format, ...) const
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{
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va_list ap;
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va_start(ap, format);
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logv_file_error(location.filename, location.first_line, format, ap);
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logv_file_error(*location.begin.filename, location.begin.line, format, ap);
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}
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YOSYS_NAMESPACE_END
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@ -28,6 +28,7 @@
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#include "kernel/rtlil.h"
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#include "kernel/fmt.h"
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#include "frontends/verilog/verilog_location.h"
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#include <stdint.h>
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#include <set>
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@ -162,13 +163,7 @@ namespace AST
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AST_BIND
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};
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struct AstSrcLocType {
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std::string filename;
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unsigned int first_line, last_line;
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unsigned int first_column, last_column;
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AstSrcLocType() : filename(""), first_line(0), last_line(0), first_column(0), last_column(0) {}
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AstSrcLocType(std::string _filename, int _first_line, int _first_column, int _last_line, int _last_column) : filename(_filename), first_line(_first_line), last_line(_last_line), first_column(_first_column), last_column(_last_column) {}
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};
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using AstSrcLocType = location;
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// convert an node type to a string (e.g. for debug output)
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std::string type2str(AstNodeType type);
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@ -407,7 +402,7 @@ namespace AST
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// this must be set by the language frontend before parsing the sources
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// the AstNode constructor then uses current_filename and get_line_num()
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// to initialize the filename and linenum properties of new nodes
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extern std::string current_filename;
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// extern std::string current_filename;
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// also set by the language frontend to control some AST processing
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extern bool sv_mode_but_global_and_used_for_literally_one_condition;
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@ -45,7 +45,7 @@ using namespace AST_INTERNAL;
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// helper function for creating RTLIL code for unary operations
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static RTLIL::SigSpec uniop2rtlil(AstNode *that, IdString type, int result_width, const RTLIL::SigSpec &arg, bool gen_attributes = true)
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{
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IdString name = stringf("%s$%s:%d$%d", type.c_str(), RTLIL::encode_filename(that->location.filename).c_str(), that->location.first_line, autoidx++);
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IdString name = stringf("%s$%s:%d$%d", type.c_str(), RTLIL::encode_filename(*that->location.begin.filename).c_str(), that->location.begin.line, autoidx++);
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RTLIL::Cell *cell = current_module->addCell(name, type);
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set_src_attr(cell, that);
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@ -77,7 +77,7 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s
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return;
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}
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IdString name = stringf("$extend$%s:%d$%d", RTLIL::encode_filename(that->location.filename).c_str(), that->location.first_line, autoidx++);
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IdString name = stringf("$extend$%s:%d$%d", RTLIL::encode_filename(*that->location.begin.filename).c_str(), that->location.begin.line, autoidx++);
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RTLIL::Cell *cell = current_module->addCell(name, ID($pos));
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set_src_attr(cell, that);
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@ -104,7 +104,7 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s
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// helper function for creating RTLIL code for binary operations
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static RTLIL::SigSpec binop2rtlil(AstNode *that, IdString type, int result_width, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)
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{
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IdString name = stringf("%s$%s:%d$%d", type.c_str(), RTLIL::encode_filename(that->location.filename).c_str(), that->location.first_line, autoidx++);
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IdString name = stringf("%s$%s:%d$%d", type.c_str(), RTLIL::encode_filename(*that->location.begin.filename).c_str(), that->location.begin.line, autoidx++);
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RTLIL::Cell *cell = current_module->addCell(name, type);
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set_src_attr(cell, that);
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@ -138,7 +138,7 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const
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log_assert(cond.size() == 1);
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std::stringstream sstr;
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sstr << "$ternary$" << RTLIL::encode_filename(that->location.filename) << ":" << that->location.first_line << "$" << (autoidx++);
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sstr << "$ternary$" << RTLIL::encode_filename(*that->location.begin.filename) << ":" << that->location.begin.line << "$" << (autoidx++);
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RTLIL::Cell *cell = current_module->addCell(sstr.str(), ID($mux));
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set_src_attr(cell, that);
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@ -195,12 +195,12 @@ struct AST_INTERNAL::LookaheadRewriter
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if (node->lookahead) {
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log_assert(node->type == AST_IDENTIFIER);
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if (!lookaheadids.count(node->str)) {
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auto wire = std::make_unique<AstNode>(AST_WIRE);
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auto wire = std::make_unique<AstNode>(node->location, AST_WIRE);
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for (auto& c : node->id2ast->children)
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wire->children.push_back(c->clone());
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wire->fixup_hierarchy_flags();
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wire->str = stringf("$lookahead%s$%d", node->str.c_str(), autoidx++);
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wire->set_attribute(ID::nosync, AstNode::mkconst_int(1, false));
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wire->set_attribute(ID::nosync, AstNode::mkconst_int(node->location, 1, false));
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wire->is_logic = true;
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while (wire->simplify(true, 1, -1, false)) { }
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lookaheadids[node->str] = make_pair(node->id2ast, wire.get());
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@ -271,6 +271,7 @@ struct AST_INTERNAL::LookaheadRewriter
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// top->dumpVlog(nullptr, "REWRITE-BEFORE> ");
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AstNode *block = nullptr;
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auto loc = top->location;
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for (auto& c : top->children)
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if (c->type == AST_BLOCK) {
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@ -284,18 +285,18 @@ struct AST_INTERNAL::LookaheadRewriter
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for (auto it : lookaheadids)
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{
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auto ref_orig = std::make_unique<AstNode>(AST_IDENTIFIER);
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auto ref_orig = std::make_unique<AstNode>(loc, AST_IDENTIFIER);
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ref_orig->str = it.second.first->str;
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ref_orig->id2ast = it.second.first;
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ref_orig->was_checked = true;
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auto ref_temp = std::make_unique<AstNode>(AST_IDENTIFIER);
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auto ref_temp = std::make_unique<AstNode>(loc, AST_IDENTIFIER);
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ref_temp->str = it.second.second->str;
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ref_temp->id2ast = it.second.second;
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ref_temp->was_checked = true;
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auto init_assign = std::make_unique<AstNode>(AST_ASSIGN_EQ, ref_temp->clone(), ref_orig->clone());
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auto final_assign = std::make_unique<AstNode>(AST_ASSIGN_LE, std::move(ref_orig), std::move(ref_temp));
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auto init_assign = std::make_unique<AstNode>(loc, AST_ASSIGN_EQ, ref_temp->clone(), ref_orig->clone());
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auto final_assign = std::make_unique<AstNode>(loc, AST_ASSIGN_LE, std::move(ref_orig), std::move(ref_temp));
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block->children.insert(block->children.begin(), std::move(init_assign));
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block->children.push_back(std::move(final_assign));
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@ -347,7 +348,7 @@ struct AST_INTERNAL::ProcessGenerator
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LookaheadRewriter la_rewriter(always.get());
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// generate process and simple root case
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proc = current_module->addProcess(stringf("$proc$%s:%d$%d", RTLIL::encode_filename(always->location.filename).c_str(), always->location.first_line, autoidx++));
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proc = current_module->addProcess(stringf("$proc$%s:%d$%d", RTLIL::encode_filename(*always->location.begin.filename).c_str(), always->location.begin.line, autoidx++));
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set_src_attr(proc, always.get());
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for (auto &attr : always->attributes) {
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if (attr.second->type != AST_CONSTANT)
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@ -723,7 +724,7 @@ struct AST_INTERNAL::ProcessGenerator
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if (ast->str == "$display" || ast->str == "$displayb" || ast->str == "$displayh" || ast->str == "$displayo" ||
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ast->str == "$write" || ast->str == "$writeb" || ast->str == "$writeh" || ast->str == "$writeo") {
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std::stringstream sstr;
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sstr << ast->str << "$" << ast->location.filename << ":" << ast->location.first_line << "$" << (autoidx++);
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sstr << ast->str << "$" << ast->location.begin.filename << ":" << ast->location.begin.line << "$" << (autoidx++);
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Wire *en = current_module->addWire(sstr.str() + "_EN", 1);
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set_src_attr(en, ast);
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@ -766,8 +767,8 @@ struct AST_INTERNAL::ProcessGenerator
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node->detectSignWidth(width, is_signed, nullptr);
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VerilogFmtArg arg = {};
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arg.filename = node->location.filename;
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arg.first_line = node->location.first_line;
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arg.filename = *node->location.begin.filename;
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arg.first_line = node->location.begin.line;
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if (node->type == AST_CONSTANT && node->is_string) {
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arg.type = VerilogFmtArg::STRING;
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arg.str = node->bitsAsConst().decode_string();
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@ -793,7 +794,7 @@ struct AST_INTERNAL::ProcessGenerator
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fmt.append_literal("\n");
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fmt.emit_rtlil(cell);
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} else if (!ast->str.empty()) {
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log_file_error(ast->location.filename, ast->location.first_line, "Found unsupported invocation of system task `%s'!\n", ast->str.c_str());
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log_file_error(*ast->location.begin.filename, ast->location.begin.line, "Found unsupported invocation of system task `%s'!\n", ast->str.c_str());
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}
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break;
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@ -813,7 +814,7 @@ struct AST_INTERNAL::ProcessGenerator
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IdString cellname;
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if (ast->str.empty())
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cellname = stringf("$%s$%s:%d$%d", flavor.c_str(), RTLIL::encode_filename(ast->location.filename).c_str(), ast->location.first_line, autoidx++);
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cellname = stringf("$%s$%s:%d$%d", flavor.c_str(), RTLIL::encode_filename(*ast->location.begin.filename).c_str(), ast->location.begin.line, autoidx++);
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else
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cellname = ast->str;
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check_unique_id(current_module, cellname, ast, "procedural assertion");
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@ -843,7 +844,7 @@ struct AST_INTERNAL::ProcessGenerator
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set_src_attr(cell, ast);
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for (auto &attr : ast->attributes) {
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if (attr.second->type != AST_CONSTANT)
|
||||
log_file_error(ast->location.filename, ast->location.first_line, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
|
||||
log_file_error(*ast->location.begin.filename, ast->location.begin.line, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
|
||||
cell->attributes[attr.first] = attr.second->asAttrConst();
|
||||
}
|
||||
cell->setParam(ID::FLAVOR, flavor);
|
||||
|
|
@ -1503,7 +1504,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
}
|
||||
|
||||
RTLIL::SigSpec sig = realAsConst(width_hint);
|
||||
log_file_warning(location.filename, location.first_line, "converting real value %e to binary %s.\n", realvalue, log_signal(sig));
|
||||
log_file_warning(*location.begin.filename, location.begin.line, "converting real value %e to binary %s.\n", realvalue, log_signal(sig));
|
||||
return sig;
|
||||
}
|
||||
|
||||
|
|
@ -1535,7 +1536,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
if (dynamic_cast<RTLIL::Binding*>(current_module)) {
|
||||
/* nothing to do here */
|
||||
} else if (flag_autowire)
|
||||
log_file_warning(location.filename, location.first_line, "Identifier `%s' is implicitly declared.\n", str.c_str());
|
||||
log_file_warning(*location.begin.filename, location.begin.line, "Identifier `%s' is implicitly declared.\n", str.c_str());
|
||||
else
|
||||
input_error("Identifier `%s' is implicitly declared and `default_nettype is set to none.\n", str.c_str());
|
||||
}
|
||||
|
|
@ -1610,7 +1611,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT)
|
||||
input_error("Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str());
|
||||
int width = abs(int(left_at_zero_ast->integer - right_at_zero_ast->integer)) + 1;
|
||||
auto fake_ast = std::make_unique<AstNode>(AST_NONE, clone(), children[0]->children.size() >= 2 ?
|
||||
auto fake_ast = std::make_unique<AstNode>(children[0]->location, AST_NONE, clone(), children[0]->children.size() >= 2 ?
|
||||
children[0]->children[1]->clone() : children[0]->children[0]->clone());
|
||||
fake_ast->children[0]->delete_children();
|
||||
if (member_node)
|
||||
|
|
@ -1640,10 +1641,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
chunk.offset = source_width - (chunk.offset + chunk.width);
|
||||
if (chunk.offset > chunk_left || chunk.offset + chunk.width < chunk_right) {
|
||||
if (chunk.width == 1)
|
||||
log_file_warning(location.filename, location.first_line, "Range select out of bounds on signal `%s': Setting result bit to undef.\n",
|
||||
log_file_warning(*location.begin.filename, location.begin.line, "Range select out of bounds on signal `%s': Setting result bit to undef.\n",
|
||||
str.c_str());
|
||||
else
|
||||
log_file_warning(location.filename, location.first_line, "Range select [%d:%d] out of bounds on signal `%s': Setting all %d result bits to undef.\n",
|
||||
log_file_warning(*location.begin.filename, location.begin.line, "Range select [%d:%d] out of bounds on signal `%s': Setting all %d result bits to undef.\n",
|
||||
children[0]->range_left, children[0]->range_right, str.c_str(), chunk.width);
|
||||
chunk = RTLIL::SigChunk(RTLIL::State::Sx, chunk.width);
|
||||
} else {
|
||||
|
|
@ -1657,10 +1658,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
chunk.offset += add_undef_bits_lsb;
|
||||
}
|
||||
if (add_undef_bits_lsb)
|
||||
log_file_warning(location.filename, location.first_line, "Range [%d:%d] select out of bounds on signal `%s': Setting %d LSB bits to undef.\n",
|
||||
log_file_warning(*location.begin.filename, location.begin.line, "Range [%d:%d] select out of bounds on signal `%s': Setting %d LSB bits to undef.\n",
|
||||
children[0]->range_left, children[0]->range_right, str.c_str(), add_undef_bits_lsb);
|
||||
if (add_undef_bits_msb)
|
||||
log_file_warning(location.filename, location.first_line, "Range [%d:%d] select out of bounds on signal `%s': Setting %d MSB bits to undef.\n",
|
||||
log_file_warning(*location.begin.filename, location.begin.line, "Range [%d:%d] select out of bounds on signal `%s': Setting %d MSB bits to undef.\n",
|
||||
children[0]->range_left, children[0]->range_right, str.c_str(), add_undef_bits_msb);
|
||||
}
|
||||
}
|
||||
|
|
@ -1934,7 +1935,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
case AST_MEMRD:
|
||||
{
|
||||
std::stringstream sstr;
|
||||
sstr << "$memrd$" << str << "$" << RTLIL::encode_filename(location.filename) << ":" << location.first_line << "$" << (autoidx++);
|
||||
sstr << "$memrd$" << str << "$" << RTLIL::encode_filename(*location.begin.filename) << ":" << location.begin.line << "$" << (autoidx++);
|
||||
|
||||
RTLIL::Cell *cell = current_module->addCell(sstr.str(), ID($memrd));
|
||||
set_src_attr(cell, this);
|
||||
|
|
@ -1972,7 +1973,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
case AST_MEMINIT:
|
||||
{
|
||||
std::stringstream sstr;
|
||||
sstr << "$meminit$" << str << "$" << RTLIL::encode_filename(location.filename) << ":" << location.first_line << "$" << (autoidx++);
|
||||
sstr << "$meminit$" << str << "$" << RTLIL::encode_filename(*location.begin.filename) << ":" << location.begin.line << "$" << (autoidx++);
|
||||
|
||||
SigSpec en_sig = children[2]->genRTLIL();
|
||||
|
||||
|
|
@ -2017,7 +2018,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
|
||||
IdString cellname;
|
||||
if (str.empty())
|
||||
cellname = stringf("$%s$%s:%d$%d", flavor.c_str(), RTLIL::encode_filename(location.filename).c_str(), location.first_line, autoidx++);
|
||||
cellname = stringf("$%s$%s:%d$%d", flavor.c_str(), RTLIL::encode_filename(*location.begin.filename).c_str(), location.begin.line, autoidx++);
|
||||
else
|
||||
cellname = str;
|
||||
check_unique_id(current_module, cellname, this, "procedural assertion");
|
||||
|
|
@ -2060,7 +2061,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
new_left.append(left[i]);
|
||||
new_right.append(right[i]);
|
||||
}
|
||||
log_file_warning(location.filename, location.first_line, "Ignoring assignment to constant bits:\n"
|
||||
log_file_warning(*location.begin.filename, location.begin.line, "Ignoring assignment to constant bits:\n"
|
||||
" old assignment: %s = %s\n new assignment: %s = %s.\n",
|
||||
log_signal(left), log_signal(right),
|
||||
log_signal(new_left), log_signal(new_right));
|
||||
|
|
@ -2095,7 +2096,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
IdString paraname = child->str.empty() ? stringf("$%d", ++para_counter) : child->str;
|
||||
const AstNode *value = child->children[0].get();
|
||||
if (value->type == AST_REALVALUE)
|
||||
log_file_warning(location.filename, location.first_line, "Replacing floating point parameter %s.%s = %f with string.\n",
|
||||
log_file_warning(*location.begin.filename, location.begin.line, "Replacing floating point parameter %s.%s = %f with string.\n",
|
||||
log_id(cell), log_id(paraname), value->realvalue);
|
||||
else if (value->type != AST_CONSTANT)
|
||||
input_error("Parameter %s.%s with non-constant value!\n",
|
||||
|
|
@ -2192,14 +2193,14 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
|
|||
int sz = children.size();
|
||||
if (str == "$info") {
|
||||
if (sz > 0)
|
||||
log_file_info(location.filename, location.first_line, "%s.\n", children[0]->str.c_str());
|
||||
log_file_info(*location.begin.filename, location.begin.line, "%s.\n", children[0]->str.c_str());
|
||||
else
|
||||
log_file_info(location.filename, location.first_line, "\n");
|
||||
log_file_info(*location.begin.filename, location.begin.line, "\n");
|
||||
} else if (str == "$warning") {
|
||||
if (sz > 0)
|
||||
log_file_warning(location.filename, location.first_line, "%s.\n", children[0]->str.c_str());
|
||||
log_file_warning(*location.begin.filename, location.begin.line, "%s.\n", children[0]->str.c_str());
|
||||
else
|
||||
log_file_warning(location.filename, location.first_line, "\n");
|
||||
log_file_warning(*location.begin.filename, location.begin.line, "\n");
|
||||
} else if (str == "$error") {
|
||||
if (sz > 0)
|
||||
input_error("%s.\n", children[0]->str.c_str());
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
2
frontends/verilog/.gitignore
vendored
2
frontends/verilog/.gitignore
vendored
|
|
@ -2,6 +2,4 @@ verilog_lexer.cc
|
|||
verilog_parser.output
|
||||
verilog_parser.tab.cc
|
||||
verilog_parser.tab.hh
|
||||
position.hh
|
||||
location.hh
|
||||
stack.hh
|
||||
|
|
|
|||
|
|
@ -3,11 +3,9 @@ GENFILES += frontends/verilog/verilog_parser.tab.cc
|
|||
GENFILES += frontends/verilog/verilog_parser.tab.hh
|
||||
GENFILES += frontends/verilog/verilog_parser.output
|
||||
GENFILES += frontends/verilog/verilog_lexer.cc
|
||||
GENFILES += frontends/verilog/location.hh
|
||||
GENFILES += frontends/verilog/position.hh
|
||||
GENFILES += frontends/verilog/stack.hh
|
||||
|
||||
frontends/verilog/verilog_parser.tab.cc: frontends/verilog/verilog_parser.y
|
||||
frontends/verilog/verilog_parser.tab.cc: frontends/verilog/verilog_parser.y frontends/verilog/verilog_location.h
|
||||
$(Q) mkdir -p $(dir $@)
|
||||
$(P) $(BISON) -Wall -Werror -o $@ -d -r all -b frontends/verilog/verilog_parser $<
|
||||
|
||||
|
|
|
|||
|
|
@ -47,7 +47,7 @@ using namespace VERILOG_FRONTEND;
|
|||
std::string ConstParser::fmt_maybe_loc(std::string msg) {
|
||||
std::string s;
|
||||
|
||||
s += stringf("%s:%d:", loc.filename, loc.first_line);
|
||||
s += stringf("%s:%d:", loc.begin.filename->c_str(), loc.begin.line);
|
||||
|
||||
s += msg;
|
||||
return s;
|
||||
|
|
|
|||
|
|
@ -33,6 +33,7 @@
|
|||
#include "verilog_frontend.h"
|
||||
#include "verilog_lexer.h"
|
||||
#include "verilog_error.h"
|
||||
#include "verilog_location.h"
|
||||
#include "preproc.h"
|
||||
#include "kernel/yosys.h"
|
||||
#include "libs/sha1/sha1.h"
|
||||
|
|
@ -277,8 +278,8 @@ struct VerilogFrontend : public Frontend {
|
|||
std::list<std::string> include_dirs;
|
||||
std::list<std::string> attributes;
|
||||
|
||||
ParseMode parse_mode;
|
||||
ParseState parse_state;
|
||||
ParseMode parse_mode = {};
|
||||
ParseState parse_state = {};
|
||||
parse_mode.sv = false;
|
||||
parse_mode.formal = false;
|
||||
parse_mode.noassert = false;
|
||||
|
|
@ -479,11 +480,6 @@ struct VerilogFrontend : public Frontend {
|
|||
break;
|
||||
}
|
||||
|
||||
VerilogLexer lexer(&parse_state, &parse_mode, &filename);
|
||||
frontend_verilog_yy::parser parser(&lexer, &parse_state, &parse_mode);
|
||||
lexer.set_debug(flag_debug_lexer);
|
||||
parser.set_debug_level(flag_debug_parser ? 1 : 0);
|
||||
|
||||
if (parse_mode.formal || !flag_nosynthesis)
|
||||
defines_map.add(parse_mode.formal ? "FORMAL" : "SYNTHESIS", "1");
|
||||
|
||||
|
|
@ -495,13 +491,9 @@ struct VerilogFrontend : public Frontend {
|
|||
parse_mode.formal ? "formal " : "", parse_mode.sv ? "SystemVerilog" : "Verilog", filename.c_str());
|
||||
|
||||
AST::sv_mode_but_global_and_used_for_literally_one_condition = parse_mode.sv;
|
||||
|
||||
AstSrcLocType top_loc = AstSrcLocType ( "read_verilog", 0, 0, 0, 0);
|
||||
parse_state.current_ast = new AST::AstNode(top_loc, AST::AST_DESIGN);
|
||||
|
||||
parse_state.lexin = f;
|
||||
std::string code_after_preproc;
|
||||
|
||||
parse_state.lexin = f;
|
||||
if (!flag_nopp) {
|
||||
code_after_preproc = frontend_verilog_preproc(*f, filename, defines_map, *design->verilog_defines, include_dirs, parse_state, parse_mode);
|
||||
if (flag_ppdump)
|
||||
|
|
@ -509,6 +501,15 @@ struct VerilogFrontend : public Frontend {
|
|||
parse_state.lexin = new std::istringstream(code_after_preproc);
|
||||
}
|
||||
|
||||
auto filename_shared = std::make_shared<std::string>(filename);
|
||||
auto top_loc = location();
|
||||
top_loc.begin.filename = filename_shared;
|
||||
parse_state.current_ast = new AST::AstNode(top_loc, AST::AST_DESIGN);
|
||||
VerilogLexer lexer(&parse_state, &parse_mode, filename_shared);
|
||||
frontend_verilog_yy::parser parser(&lexer, &parse_state, &parse_mode);
|
||||
lexer.set_debug(flag_debug_lexer);
|
||||
parser.set_debug_level(flag_debug_parser ? 1 : 0);
|
||||
|
||||
// make package typedefs available to parser
|
||||
add_package_types(parse_state.pkg_user_types, design->verilog_packages);
|
||||
|
||||
|
|
|
|||
|
|
@ -5,6 +5,7 @@
|
|||
#include "frontends/ast/ast.h"
|
||||
#include "frontends/verilog/verilog_parser.tab.hh"
|
||||
#include <string>
|
||||
#include <memory>
|
||||
|
||||
YOSYS_NAMESPACE_BEGIN
|
||||
|
||||
|
|
@ -15,7 +16,7 @@ namespace VERILOG_FRONTEND {
|
|||
ParseMode* mode;
|
||||
public:
|
||||
parser::location_type out_loc; // TODO private?
|
||||
VerilogLexer(ParseState* e, ParseMode* m, std::string* filename) : frontend_verilog_yyFlexLexer(e->lexin), extra(e), mode(m) {
|
||||
VerilogLexer(ParseState* e, ParseMode* m, std::shared_ptr<string> filename) : frontend_verilog_yyFlexLexer(e->lexin), extra(e), mode(m) {
|
||||
out_loc.begin.filename = filename;
|
||||
}
|
||||
~VerilogLexer() override {}
|
||||
|
|
@ -27,7 +28,8 @@ namespace VERILOG_FRONTEND {
|
|||
return parser::make_FRONTEND_VERILOG_YYEOF(out_loc);
|
||||
}
|
||||
private:
|
||||
std::vector<std::string> fn_stack;
|
||||
std::shared_ptr<std::string> current_filename;
|
||||
std::vector<std::shared_ptr<std::string>> fn_stack;
|
||||
std::vector<int> ln_stack;
|
||||
int LexerInput(char* buf, int max_size) override {
|
||||
return readsome(*extra->lexin, buf, max_size);
|
||||
|
|
|
|||
|
|
@ -50,8 +50,10 @@
|
|||
|
||||
#include "frontends/verilog/verilog_lexer.h"
|
||||
#include "frontends/ast/ast.h"
|
||||
#include "frontends/verilog/verilog_location.h"
|
||||
#include "kernel/log.h"
|
||||
#include <vector>
|
||||
#include <memory>
|
||||
|
||||
USING_YOSYS_NAMESPACE
|
||||
using namespace AST;
|
||||
|
|
@ -73,7 +75,7 @@ YOSYS_NAMESPACE_END
|
|||
if (mode->sv) return _tok; \
|
||||
log("Lexer warning: The SystemVerilog keyword `%s' (at %s:%d) is not "\
|
||||
"recognized unless read_verilog is called with -sv!\n", YYText(), \
|
||||
AST::current_filename.c_str(), yylineno); \
|
||||
current_filename->c_str(), yylineno); \
|
||||
string_t val = std::make_unique<std::string>(std::string("\\") + YYText()); \
|
||||
return parser::make_TOK_ID(std::move(val), out_loc);
|
||||
|
||||
|
|
@ -85,16 +87,17 @@ YOSYS_NAMESPACE_END
|
|||
// result = readsome(*extra->lexin, buf, max_size)
|
||||
|
||||
#define YY_USER_ACTION \
|
||||
out_loc.begin = out_loc.end; \
|
||||
for(int i = 0; YYText()[i] != '\0'; ++i){ \
|
||||
if(YYText()[i] == '\n') { \
|
||||
out_loc.end.line++; \
|
||||
out_loc.end.column = 1; \
|
||||
} \
|
||||
else { \
|
||||
out_loc.end.column++; \
|
||||
} \
|
||||
}
|
||||
out_loc.step(); \
|
||||
for(int i = 0; YYText()[i] != '\0'; ++i){ \
|
||||
if(YYText()[i] == '\n') { \
|
||||
out_loc.lines(); \
|
||||
} \
|
||||
else { \
|
||||
out_loc.columns(); \
|
||||
} \
|
||||
} \
|
||||
out_loc.begin.filename = current_filename; \
|
||||
out_loc.end.filename = current_filename;
|
||||
|
||||
#define YY_BREAK \
|
||||
break;
|
||||
|
|
@ -175,11 +178,12 @@ TIME_SCALE_SUFFIX [munpf]?s
|
|||
<INITIAL,SYNOPSYS_TRANSLATE_OFF>"`file_push "[^\n]* {
|
||||
fn_stack.push_back(current_filename);
|
||||
ln_stack.push_back(yylineno);
|
||||
current_filename = YYText()+11;
|
||||
if (!current_filename.empty() && current_filename.front() == '"')
|
||||
current_filename = current_filename.substr(1);
|
||||
if (!current_filename.empty() && current_filename.back() == '"')
|
||||
current_filename = current_filename.substr(0, current_filename.size()-1);
|
||||
std::string filename = YYText()+11;
|
||||
if (!filename.empty() && filename.front() == '"')
|
||||
filename = filename.substr(1);
|
||||
if (!filename.empty() && filename.back() == '"')
|
||||
filename = filename.substr(0, filename.size()-1);
|
||||
current_filename = std::make_shared<std::string>(filename);
|
||||
yylineno = (0);
|
||||
out_loc.begin.line = out_loc.end.line = 0;
|
||||
}
|
||||
|
|
@ -201,7 +205,7 @@ TIME_SCALE_SUFFIX [munpf]?s
|
|||
while (*p == ' ' || *p == '\t') p++;
|
||||
const char *q = *p ? p + 1 : p;
|
||||
while (*q && *q != '"') q++;
|
||||
current_filename = std::string(p).substr(1, q-p-1);
|
||||
current_filename = std::make_shared<std::string>(std::string(p).substr(1, q-p-1));
|
||||
}
|
||||
|
||||
"`file_notfound "[^\n]* {
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -5704,7 +5704,7 @@ bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::stri
|
|||
{
|
||||
cover("kernel.rtlil.sigspec.parse");
|
||||
|
||||
AST::current_filename = "input";
|
||||
// AST::current_filename = "input";
|
||||
|
||||
std::vector<std::string> tokens;
|
||||
sigspec_parse_split(tokens, str, ',');
|
||||
|
|
@ -5720,7 +5720,7 @@ bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::stri
|
|||
|
||||
if (('0' <= netname[0] && netname[0] <= '9') || netname[0] == '\'') {
|
||||
cover("kernel.rtlil.sigspec.parse.const");
|
||||
VERILOG_FRONTEND::ConstParser p;
|
||||
VERILOG_FRONTEND::ConstParser p{location()};
|
||||
auto ast = p.const2ast(netname);
|
||||
if (ast == nullptr)
|
||||
return false;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue