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yosys/frontends
garytwong 834a7294b7
verilog: fix string literal regular expression (#5187)
* verilog: fix string literal regular expression.

A backslash was improperly quoted, causing string literal matching
to fail when the final token before a closing quote was an escaped
backslash.

* verilog: add regression test for string literal regex bug.

Test for bug triggered by escaped backslash immediately before
closing quote (introduced in ca7d94af and fixed by 40aa7eaf).
2025-06-19 12:41:18 -04:00
..
aiger rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
aiger2 aiger2: Clean debug print 2024-12-10 14:27:55 +01:00
ast Merge pull request #5163 from YosysHQ/emil/fix-single-bit-vector-leak 2025-06-04 17:00:54 +02:00
blif rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
json fix handling of escaped chars in json backend and frontend 2022-02-18 17:13:09 +01:00
liberty Liberty file caching with new libcache command 2025-04-03 13:39:35 +02:00
rpc Fitting help messages to 80 character width 2022-08-24 10:40:57 +12:00
rtlil read_rtlil: warn on assigns after switches in case rules 2024-11-21 22:41:13 +01:00
verific downgrade verific warnings about common coding styles 2025-06-06 16:30:50 +02:00
verilog verilog: fix string literal regular expression (#5187) 2025-06-19 12:41:18 -04:00