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Merge pull request #5102 from YosysHQ/krys/verilog_no_select
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7b0c1fe491
1 changed files with 1 additions and 1 deletions
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@ -753,7 +753,7 @@ struct VerilogFileList : public Pass {
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break;
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}
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extra_args(args, argidx, design);
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extra_args(args, argidx, design, false);
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}
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} VerilogFilelist;
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