Emil J. Tywoniak
6f2053fc90
verilog_lexer: refactor
2025-08-08 13:03:02 +02:00
Emil J. Tywoniak
50c5956187
ast: refactor
2025-08-08 13:03:02 +02:00
Emil J. Tywoniak
32792815eb
ast: remove null_check as dead code
2025-08-08 12:32:43 +02:00
Emil J. Tywoniak
5e8986be4f
simplify: simplify
2025-08-08 12:31:40 +02:00
Emil J. Tywoniak
4f77113960
simplify: std::gcd
2025-08-08 12:31:13 +02:00
Krystine Sherwin
c634a4c926
simplify.cc: Drop unused debug prints
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At least the ones added by this PR. There are some unused debug prints that are *changed* by this PR, but I've left them.
2025-08-08 17:14:31 +12:00
Krystine Sherwin
5be7a91149
frontends/ast: More usage of auto
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For consistency.
2025-08-08 17:10:16 +12:00
Krystine Sherwin
2f9140d3ad
docs: Update ubuntu apt-get
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Also mention CXXSTD fix for cygwin.
2025-08-08 14:00:53 +12:00
Emil J. Tywoniak
7047bc26b3
preproc: formatting
2025-07-19 22:57:53 +02:00
Emil J. Tywoniak
e77252ce8d
verilog_lexer, verilog_parser: remove comment
2025-07-19 22:56:48 +02:00
Emil J. Tywoniak
6b59d05282
verilog_lexer: fix fallthrough warning
2025-07-19 22:53:02 +02:00
Emil J
588c5d5a57
verilog_lexer: remove comment
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Co-authored-by: KrystalDelusion <93062060+KrystalDelusion@users.noreply.github.com>
2025-07-19 22:46:17 +02:00
Emil J. Tywoniak
66a9fc9fe0
preproc: formatting
2025-07-19 22:45:19 +02:00
Emil J. Tywoniak
6e011d1948
fixup! readme, verilog_parser: bison 3.8 and ubuntu 22.04 example
2025-07-19 22:40:45 +02:00
Emil J. Tywoniak
540623a513
Revert "CI: bump flex and bison on Windows"
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This reverts commit efbc138ced
2025-07-19 22:39:55 +02:00
Emil J
112b22728d
rtlil: remove comment
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Co-authored-by: KrystalDelusion <93062060+KrystalDelusion@users.noreply.github.com>
2025-07-19 22:21:17 +02:00
Krystine Sherwin
8044b558e6
Add flex lib to vcxsrc include dirs
2025-07-18 10:42:08 +12:00
Krystine Sherwin
65e026f4df
Sneak FlexLexer.h into VS build
2025-07-18 10:42:08 +12:00
Catherine
3b80afa26e
CI: fix typo
2025-07-17 12:15:47 +00:00
Catherine
5cb3fc631b
CI: install flex for WASI builds.
2025-07-17 12:03:39 +00:00
Emil J. Tywoniak
b5be4b9209
fixup! CI: sneak FlexLexer.h into the WASI sysroot
2025-07-14 22:16:46 +02:00
Emil J. Tywoniak
efbc138ced
CI: bump flex and bison on Windows
2025-07-14 22:14:11 +02:00
Emil J. Tywoniak
26e592e798
CI: sneak FlexLexer.h into the WASI sysroot
2025-07-14 21:45:41 +02:00
Emil J. Tywoniak
ca24169659
verilog: fix build dependency graph
2025-07-10 23:59:54 +02:00
Gary Wong
e17ed5df88
verilog: add support for SystemVerilog string literals.
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Differences are new escape sequences (including escaped newline
continuations and hex escapes) and triple-quoted literals.
2025-07-10 23:28:22 +02:00
garytwong
a519390fc4
verilog: fix string literal regular expression ( #5187 )
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* verilog: fix string literal regular expression.
A backslash was improperly quoted, causing string literal matching
to fail when the final token before a closing quote was an escaped
backslash.
* verilog: add regression test for string literal regex bug.
Test for bug triggered by escaped backslash immediately before
closing quote (introduced in ca7d94af40aa7eaf
2025-07-10 23:16:50 +02:00
Emil J. Tywoniak
e690fb59f1
docs: fix verilog frontend internals
2025-07-10 21:15:50 +02:00
Emil J. Tywoniak
56058b3ed4
read_verilog, ast: use unified locations in errors and simplify dependencies
2025-07-10 21:15:50 +02:00
Emil J. Tywoniak
41d9a1b88e
readme, verilog_parser: bison 3.8 and ubuntu 22.04 example
2025-07-10 21:15:50 +02:00
Krystine Sherwin
7e026d824a
dpicall.cc: Fix sans-plugin function call
2025-07-10 21:15:50 +02:00
Krystine Sherwin
cf0f72dbd7
Makefile: Add flex lib/include for brew
2025-07-10 21:15:50 +02:00
Krystine Sherwin
a2b2188a7f
preproc.cc: Use full path for generated file
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Fixes out-of-tree builds.
2025-07-10 21:15:50 +02:00
Krystine Sherwin
b90622b7ed
docs/verilog_frontend.rst: Fix indentation
2025-07-10 21:15:50 +02:00
Krystine Sherwin
7b5035e0c4
preproc depends on parser
2025-07-10 21:15:50 +02:00
Krystine Sherwin
c70224a68a
Add libfl-dev
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Should fix the missing `<FlexLexer.h>` error.
2025-07-10 21:15:50 +02:00
Emil J. Tywoniak
040d717ad7
fixup! fixup! ast, read_verilog: unify location types, reduce filename copying
2025-07-10 21:15:50 +02:00
Emil J. Tywoniak
ed0582c9f2
fixup! ast, read_verilog: unify location types, reduce filename copying
2025-07-10 21:15:50 +02:00
Emil J. Tywoniak
81e5270484
ast, read_verilog: unify location types, reduce filename copying
2025-07-10 21:15:50 +02:00
Emil J. Tywoniak
b276fb6616
neater errors, lost in the sauce of source
2025-07-10 21:15:50 +02:00
Emil J. Tywoniak
88800a16ea
ast, read_verilog: refactoring
2025-07-10 21:15:50 +02:00
Emil J. Tywoniak
31002cf259
ast: fix new memory safety bugs from rebase
2025-07-10 21:15:50 +02:00
Emil J. Tywoniak
6cb789b2c2
ast: ownership for string values
2025-07-10 21:15:50 +02:00
Emil J. Tywoniak
8a873a7724
ast, read_verilog: ownership in AST, use C++ styles for parser and lexer
2025-07-10 21:15:50 +02:00
Emil J. Tywoniak
bb08919105
Revert "verilog: fix string literal regular expression ( #5187 )"
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This reverts commit 834a7294b7
2025-07-10 21:15:38 +02:00
Emil J. Tywoniak
dc204dc909
Revert "verilog: add support for SystemVerilog string literals."
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This reverts commit 5feb1a1752
2025-07-10 21:14:38 +02:00
Emil J. Tywoniak
e0822c048e
Revert "verilog: fix parser "if" memory errors."
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This reverts commit 34a2abeddb
2025-07-10 21:13:28 +02:00
Emil J
dfe86b50d8
Merge pull request #5217 from rocallahan/fix-importSigSpecWorker-leak
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Fix space leak in `SatGen::importSigSpecWorker()` by avoiding `log_id…
2025-07-10 19:56:56 +02:00
Emil J
14aad097f0
Merge pull request #5190 from YosysHQ/emil/dfflibmap-fix-negated-next_state
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dfflibmap: propagate negated next_state to output correctly
2025-07-10 19:50:02 +02:00
Emil J. Tywoniak
7fe817c52f
dfflibmap: test negated state next_state with mixed polarities
2025-07-10 18:54:43 +02:00
N. Engelhardt
02323295b0
Merge pull request #5179 from YosysHQ/krys/assert2cover
2025-07-10 14:53:22 +02:00
