1397 commits

Author	SHA1	Message	Date
Clifford Wolf	a6c96b986b	Added Yosys::{dict,nodict,vector} container types	2014-12-26 10:53:21 +01:00
Clifford Wolf	e8c12e5f0c	Various fixes and improvements in "write_smt2 -bv"	2014-12-25 20:28:34 +01:00
Clifford Wolf	68233baa1f	Various fixes and improvements in write_smt2	2014-12-25 17:52:31 +01:00
Clifford Wolf	95f17dbab0	Added support for most BV cell types to write_smt2	2014-12-25 15:37:02 +01:00
Clifford Wolf	1c3d51375f	Added "write_smt2 -bv" and other write_smt2 improvements	2014-12-25 13:30:20 +01:00
Clifford Wolf	e548483c91	Added write_smt2 (only gate level logic supported so far)	2014-12-24 16:17:57 +01:00
Clifford Wolf	edb3c9d0c4	Renamed extend() to extend_xx(), changed most users to extend_u0()	2014-12-24 09:51:17 +01:00
Clifford Wolf	5df192e71c	Added $dffe support to write_verilog	2014-12-20 00:03:20 +01:00
Clifford Wolf	30de490d86	Fixed another bug in write_blif handling of $lut cells	2014-12-19 17:54:44 +01:00
Clifford Wolf	b95051fb70	Fixed writing of $lut cells in BLIF backend	2014-12-17 11:13:57 +01:00
Clifford Wolf	e01254d824	Added "write_blif -undef" and support for special "-" true/false/undef type	2014-12-14 18:00:38 +01:00
Clifford Wolf	59d11978fc	Added "write_blif -blackbox" ... based on code by Eddie Hung from 1e481661cb	2014-12-14 17:45:03 +01:00
Clifford Wolf	32dce4a870	Added "blif -unbuf" feature	2014-12-14 17:37:46 +01:00
Clifford Wolf	fe829bdbdc	Added log_warning() API	2014-11-09 10:44:23 +01:00
Clifford Wolf	461594bb83	Fixed generation of temp names in verilog backend	2014-11-07 14:40:06 +01:00
Clifford Wolf	4569a747f8	Renamed SIZE() to GetSize() because of name collision on Win32	2014-10-10 17:07:24 +02:00
Clifford Wolf	f9a307a50b	namespace Yosys	2014-09-27 16:17:53 +02:00
Ahmed Irfan	d3c67ad9b6	Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor ... added case for memwr cell that is used in muxes (same cell is used more than one time) corrected bug for xnor and logic_not added pmux cell translation Conflicts: backends/btor/btor.cc	2014-09-22 11:35:04 +02:00
Clifford Wolf	309623ff17	Sorting of object names in ilang backend	2014-09-19 15:50:34 +02:00
ahmedirfan1983	b783dbe148	fixed memory next issue, when same memory is written in different case statement ... fixed reduce_xnor, logic_not bug translation bug	2014-09-18 11:19:48 +02:00
Clifford Wolf	9329a76818	Various bug fixes (related to $macc model testing)	2014-09-06 20:30:46 +02:00
Ruben Undheim	79cbf9067c	Corrected spelling mistakes found by lintian	2014-09-06 08:47:06 +02:00
Clifford Wolf	8927aa6148	Removed $bu0 cell type	2014-09-04 02:07:52 +02:00
Clifford Wolf	b9cb483f3e	Using $pos models for $bu0	2014-09-03 21:20:59 +02:00
Ahmed Irfan	2446b6fbef	added $pmux cell translation	2014-09-02 14:47:51 +02:00
Clifford Wolf	e07698818d	Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::data	2014-09-01 11:36:02 +02:00
Clifford Wolf	19cff41eb4	Changed frontend-api from FILE to std::istream	2014-08-23 15:03:55 +02:00
Clifford Wolf	5dce303a2a	Changed backend-api from FILE to std::ostream	2014-08-23 13:54:21 +02:00
Clifford Wolf	f82c978e08	Fixed AOI/OAI expr handling in verilog backend	2014-08-16 22:05:09 +02:00
Clifford Wolf	47c2637a96	Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_	2014-08-16 18:29:39 +02:00
Clifford Wolf	b64b38eea2	Renamed $lut ports to follow A-Y naming scheme	2014-08-15 14:18:40 +02:00
Clifford Wolf	f092b50148	Renamed $_INV_ cell type to $_NOT_	2014-08-15 14:11:40 +02:00
Clifford Wolf	746aac540b	Refactoring of CellType class	2014-08-14 15:46:51 +02:00
Clifford Wolf	88cf00ce78	Be more conservative with printing decimal numbers in verilog backend	2014-08-02 21:54:02 +02:00
Clifford Wolf	ca1b5d50e0	Improved verilog output for ordinary $mux cells	2014-08-02 21:10:08 +02:00
Clifford Wolf	04727c7e0f	No implicit conversion from IdString to anything else	2014-08-02 18:58:40 +02:00
Clifford Wolf	b9bd22b8c8	More cleanups related to RTLIL::IdString usage	2014-08-02 13:19:57 +02:00
Clifford Wolf	cdae8abe16	Renamed port access function on RTLIL::Cell, added param access functions	2014-07-31 16:38:54 +02:00
Clifford Wolf	1cb25c05b3	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	2014-07-31 13:19:47 +02:00
Clifford Wolf	e6df25bf74	Renamed "write_autotest" to "test_autotb" and moved to passes/tests/	2014-07-29 21:12:50 +02:00
Clifford Wolf	397b00252d	Added $shift and $shiftx cell types (needed for correct part select behavior)	2014-07-29 16:35:13 +02:00
Clifford Wolf	27a872d1e7	Added support for "upto" wires to Verilog front- and back-end	2014-07-28 14:25:03 +02:00
Clifford Wolf	3c45277ee0	Added wire->upto flag for signals such as "wire [0:7] x;"	2014-07-28 12:12:13 +02:00
Clifford Wolf	7bd2d1064f	Using log_assert() instead of assert()	2014-07-28 11:27:48 +02:00
Clifford Wolf	10e5791c5e	Refactoring: Renamed RTLIL::Design::modules to modules_	2014-07-27 11:18:30 +02:00
Clifford Wolf	4c4b602156	Refactoring: Renamed RTLIL::Module::cells to cells_	2014-07-27 01:51:45 +02:00
Clifford Wolf	f9946232ad	Refactoring: Renamed RTLIL::Module::wires to wires_	2014-07-27 01:49:51 +02:00
Clifford Wolf	3f4e3ca8ad	More RTLIL::Cell API usage cleanups	2014-07-26 16:14:02 +02:00
Clifford Wolf	97a59851a6	Added RTLIL::Cell::has(portname)	2014-07-26 16:11:28 +02:00
Clifford Wolf	f8fdc47d33	Manual fixes for new cell connections API	2014-07-26 15:58:23 +02:00