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Renamed port access function on RTLIL::Cell, added param access functions

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This commit is contained in:
Clifford Wolf 2014-07-31 16:38:54 +02:00
parent b5a9e51b96
commit cdae8abe16
46 changed files with 1086 additions and 1059 deletions
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20
backends/blif/blif.cc
View file

@ -145,56 +145,56 @@ struct BlifDumper
if (!config->icells_mode && cell->type == "$_INV_") {
fprintf(f, ".names %s %s\n0 1\n",
cstr(cell->get("\\A")), cstr(cell->get("\\Y")));
cstr(cell->getPort("\\A")), cstr(cell->getPort("\\Y")));
continue;
}
if (!config->icells_mode && cell->type == "$_AND_") {
fprintf(f, ".names %s %s %s\n11 1\n",
cstr(cell->get("\\A")), cstr(cell->get("\\B")), cstr(cell->get("\\Y")));
cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), cstr(cell->getPort("\\Y")));
continue;
}
if (!config->icells_mode && cell->type == "$_OR_") {
fprintf(f, ".names %s %s %s\n1- 1\n-1 1\n",
cstr(cell->get("\\A")), cstr(cell->get("\\B")), cstr(cell->get("\\Y")));
cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), cstr(cell->getPort("\\Y")));
continue;
}
if (!config->icells_mode && cell->type == "$_XOR_") {
fprintf(f, ".names %s %s %s\n10 1\n01 1\n",
cstr(cell->get("\\A")), cstr(cell->get("\\B")), cstr(cell->get("\\Y")));
cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")), cstr(cell->getPort("\\Y")));
continue;
}
if (!config->icells_mode && cell->type == "$_MUX_") {
fprintf(f, ".names %s %s %s %s\n1-0 1\n-11 1\n",
cstr(cell->get("\\A")), cstr(cell->get("\\B")),
cstr(cell->get("\\S")), cstr(cell->get("\\Y")));
cstr(cell->getPort("\\A")), cstr(cell->getPort("\\B")),
cstr(cell->getPort("\\S")), cstr(cell->getPort("\\Y")));
continue;
}
if (!config->icells_mode && cell->type == "$_DFF_N_") {
fprintf(f, ".latch %s %s fe %s\n",
cstr(cell->get("\\D")), cstr(cell->get("\\Q")), cstr(cell->get("\\C")));
cstr(cell->getPort("\\D")), cstr(cell->getPort("\\Q")), cstr(cell->getPort("\\C")));
continue;
}
if (!config->icells_mode && cell->type == "$_DFF_P_") {
fprintf(f, ".latch %s %s re %s\n",
cstr(cell->get("\\D")), cstr(cell->get("\\Q")), cstr(cell->get("\\C")));
cstr(cell->getPort("\\D")), cstr(cell->getPort("\\Q")), cstr(cell->getPort("\\C")));
continue;
}
if (!config->icells_mode && cell->type == "$lut") {
fprintf(f, ".names");
auto &inputs = cell->get("\\I");
auto &inputs = cell->getPort("\\I");
auto width = cell->parameters.at("\\WIDTH").as_int();
log_assert(inputs.size() == width);
for (int i = 0; i < inputs.size(); i++) {
fprintf(f, " %s", cstr(inputs.extract(i, 1)));
}
auto &output = cell->get("\\O");
auto &output = cell->getPort("\\O");
log_assert(output.size() == 1);
fprintf(f, " %s", cstr(output));
fprintf(f, "\n");

68
backends/btor/btor.cc
View file

@ -389,8 +389,8 @@ struct BtorDumper
if(cell->type == "$assert")
{
log("writing assert cell - %s\n", cstr(cell->type));
const RTLIL::SigSpec* expr = &cell->get(RTLIL::IdString("\\A"));
const RTLIL::SigSpec* en = &cell->get(RTLIL::IdString("\\EN"));
const RTLIL::SigSpec* expr = &cell->getPort(RTLIL::IdString("\\A"));
const RTLIL::SigSpec* en = &cell->getPort(RTLIL::IdString("\\EN"));
log_assert(expr->size() == 1);
log_assert(en->size() == 1);
int expr_line = dump_sigspec(expr, 1);
@ -422,7 +422,7 @@ struct BtorDumper
int w = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
int output_width = cell->parameters.at(RTLIL::IdString("\\Y_WIDTH")).as_int();
w = w>output_width ? w:output_width; //padding of w
int l = dump_sigspec(&cell->get(RTLIL::IdString("\\A")), w);
int l = dump_sigspec(&cell->getPort(RTLIL::IdString("\\A")), w);
int cell_line = l;
if(cell->type != "$pos")
{
@ -446,7 +446,7 @@ struct BtorDumper
int w = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
int output_width = cell->parameters.at(RTLIL::IdString("\\Y_WIDTH")).as_int();
log_assert(output_width == 1);
int l = dump_sigspec(&cell->get(RTLIL::IdString("\\A")), w);
int l = dump_sigspec(&cell->getPort(RTLIL::IdString("\\A")), w);
if(cell->type == "$logic_not" && w > 1)
{
++line_num;
@ -483,8 +483,8 @@ struct BtorDumper
l1_width = l1_width > l2_width ? l1_width : l2_width;
l2_width = l2_width > l1_width ? l2_width : l1_width;
int l1 = dump_sigspec(&cell->get(RTLIL::IdString("\\A")), l1_width);
int l2 = dump_sigspec(&cell->get(RTLIL::IdString("\\B")), l2_width);
int l1 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\A")), l1_width);
int l2 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\B")), l2_width);
++line_num;
std::string op = cell_type_translation.at(cell->type);
@ -517,8 +517,8 @@ struct BtorDumper
l1_width = l1_width > l2_width ? l1_width : l2_width;
l2_width = l2_width > l1_width ? l2_width : l1_width;
int l1 = dump_sigspec(&cell->get(RTLIL::IdString("\\A")), l1_width);
int l2 = dump_sigspec(&cell->get(RTLIL::IdString("\\B")), l2_width);
int l1 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\A")), l1_width);
int l2 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\B")), l2_width);
++line_num;
std::string op = cell_type_translation.at(cell->type);
@ -552,8 +552,8 @@ struct BtorDumper
l1_width = pow(2, ceil(log(l1_width)/log(2)));
int l2_width = cell->parameters.at(RTLIL::IdString("\\B_WIDTH")).as_int();
//log_assert(l2_width <= ceil(log(l1_width)/log(2)) );
int l1 = dump_sigspec(&cell->get(RTLIL::IdString("\\A")), l1_width);
int l2 = dump_sigspec(&cell->get(RTLIL::IdString("\\B")), ceil(log(l1_width)/log(2)));
int l1 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\A")), l1_width);
int l2 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\B")), ceil(log(l1_width)/log(2)));
int cell_output = ++line_num;
str = stringf ("%d %s %d %d %d", line_num, cell_type_translation.at(cell->type).c_str(), l1_width, l1, l2);
fprintf(f, "%s\n", str.c_str());
@ -561,7 +561,7 @@ struct BtorDumper
if(l2_width > ceil(log(l1_width)/log(2)))
{
int extra_width = l2_width - ceil(log(l1_width)/log(2));
l2 = dump_sigspec(&cell->get(RTLIL::IdString("\\B")), l2_width);
l2 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\B")), l2_width);
++line_num;
str = stringf ("%d slice %d %d %d %d;6", line_num, extra_width, l2, l2_width-1, l2_width-extra_width);
fprintf(f, "%s\n", str.c_str());
@ -594,8 +594,8 @@ struct BtorDumper
log("writing binary cell - %s\n", cstr(cell->type));
int output_width = cell->parameters.at(RTLIL::IdString("\\Y_WIDTH")).as_int();
log_assert(output_width == 1);
int l1 = dump_sigspec(&cell->get(RTLIL::IdString("\\A")), output_width);
int l2 = dump_sigspec(&cell->get(RTLIL::IdString("\\B")), output_width);
int l1 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\A")), output_width);
int l2 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\B")), output_width);
int l1_width = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
int l2_width = cell->parameters.at(RTLIL::IdString("\\B_WIDTH")).as_int();
if(l1_width >1)
@ -630,9 +630,9 @@ struct BtorDumper
{
log("writing mux cell\n");
int output_width = cell->parameters.at(RTLIL::IdString("\\WIDTH")).as_int();
int l1 = dump_sigspec(&cell->get(RTLIL::IdString("\\A")), output_width);
int l2 = dump_sigspec(&cell->get(RTLIL::IdString("\\B")), output_width);
int s = dump_sigspec(&cell->get(RTLIL::IdString("\\S")), 1);
int l1 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\A")), output_width);
int l2 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\B")), output_width);
int s = dump_sigspec(&cell->getPort(RTLIL::IdString("\\S")), 1);
++line_num;
str = stringf ("%d %s %d %d %d %d",
line_num, cell_type_translation.at(cell->type).c_str(), output_width, s, l2, l1);//if s is 0 then l1, if s is 1 then l2 //according to the implementation of mux cell
@ -646,10 +646,10 @@ struct BtorDumper
log("writing cell - %s\n", cstr(cell->type));
int output_width = cell->parameters.at(RTLIL::IdString("\\WIDTH")).as_int();
log(" - width is %d\n", output_width);
int cond = dump_sigspec(&cell->get(RTLIL::IdString("\\CLK")), 1);
int cond = dump_sigspec(&cell->getPort(RTLIL::IdString("\\CLK")), 1);
bool polarity = cell->parameters.at(RTLIL::IdString("\\CLK_POLARITY")).as_bool();
const RTLIL::SigSpec* cell_output = &cell->get(RTLIL::IdString("\\Q"));
int value = dump_sigspec(&cell->get(RTLIL::IdString("\\D")), output_width);
const RTLIL::SigSpec* cell_output = &cell->getPort(RTLIL::IdString("\\Q"));
int value = dump_sigspec(&cell->getPort(RTLIL::IdString("\\D")), output_width);
unsigned start_bit = 0;
for(unsigned i=0; i<cell_output->chunks().size(); ++i)
{
@ -667,9 +667,9 @@ struct BtorDumper
}
if(cell->type == "$dffsr")
{
int sync_reset = dump_sigspec(&cell->get(RTLIL::IdString("\\CLR")), 1);
int sync_reset = dump_sigspec(&cell->getPort(RTLIL::IdString("\\CLR")), 1);
bool sync_reset_pol = cell->parameters.at(RTLIL::IdString("\\CLR_POLARITY")).as_bool();
int sync_reset_value = dump_sigspec(&cell->get(RTLIL::IdString("\\SET")),
int sync_reset_value = dump_sigspec(&cell->getPort(RTLIL::IdString("\\SET")),
output_width);
bool sync_reset_value_pol = cell->parameters.at(RTLIL::IdString("\\SET_POLARITY")).as_bool();
++line_num;
@ -687,7 +687,7 @@ struct BtorDumper
int next = line_num;
if(cell->type == "$adff")
{
int async_reset = dump_sigspec(&cell->get(RTLIL::IdString("\\ARST")), 1);
int async_reset = dump_sigspec(&cell->getPort(RTLIL::IdString("\\ARST")), 1);
bool async_reset_pol = cell->parameters.at(RTLIL::IdString("\\ARST_POLARITY")).as_bool();
int async_reset_value = dump_const(&cell->parameters.at(RTLIL::IdString("\\ARST_VALUE")),
output_width, 0);
@ -712,7 +712,7 @@ struct BtorDumper
str = cell->parameters.at(RTLIL::IdString("\\MEMID")).decode_string();
int mem = dump_memory(module->memories.at(RTLIL::IdString(str.c_str())));
int address_width = cell->parameters.at(RTLIL::IdString("\\ABITS")).as_int();
int address = dump_sigspec(&cell->get(RTLIL::IdString("\\ADDR")), address_width);
int address = dump_sigspec(&cell->getPort(RTLIL::IdString("\\ADDR")), address_width);
int data_width = cell->parameters.at(RTLIL::IdString("\\WIDTH")).as_int();
++line_num;
str = stringf("%d read %d %d %d", line_num, data_width, mem, address);
@ -724,13 +724,13 @@ struct BtorDumper
log("writing memwr cell\n");
if (cell->parameters.at("\\CLK_ENABLE").as_bool() == false)
log_error("The btor backen does not support $memwr cells without built-in registers. Run memory_dff (but with -wr_only).\n");
int clk = dump_sigspec(&cell->get(RTLIL::IdString("\\CLK")), 1);
int clk = dump_sigspec(&cell->getPort(RTLIL::IdString("\\CLK")), 1);
bool polarity = cell->parameters.at(RTLIL::IdString("\\CLK_POLARITY")).as_bool();
int enable = dump_sigspec(&cell->get(RTLIL::IdString("\\EN")), 1);
int enable = dump_sigspec(&cell->getPort(RTLIL::IdString("\\EN")), 1);
int address_width = cell->parameters.at(RTLIL::IdString("\\ABITS")).as_int();
int address = dump_sigspec(&cell->get(RTLIL::IdString("\\ADDR")), address_width);
int address = dump_sigspec(&cell->getPort(RTLIL::IdString("\\ADDR")), address_width);
int data_width = cell->parameters.at(RTLIL::IdString("\\WIDTH")).as_int();
int data = dump_sigspec(&cell->get(RTLIL::IdString("\\DATA")), data_width);
int data = dump_sigspec(&cell->getPort(RTLIL::IdString("\\DATA")), data_width);
str = cell->parameters.at(RTLIL::IdString("\\MEMID")).decode_string();
int mem = dump_memory(module->memories.at(RTLIL::IdString(str.c_str())));
++line_num;
@ -759,11 +759,11 @@ struct BtorDumper
else if(cell->type == "$slice")
{
log("writing slice cell\n");
const RTLIL::SigSpec* input = &cell->get(RTLIL::IdString("\\A"));
const RTLIL::SigSpec* input = &cell->getPort(RTLIL::IdString("\\A"));
int input_width = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
log_assert(input->size() == input_width);
int input_line = dump_sigspec(input, input_width);
const RTLIL::SigSpec* output = &cell->get(RTLIL::IdString("\\Y"));
const RTLIL::SigSpec* output = &cell->getPort(RTLIL::IdString("\\Y"));
int output_width = cell->parameters.at(RTLIL::IdString("\\Y_WIDTH")).as_int();
log_assert(output->size() == output_width);
int offset = cell->parameters.at(RTLIL::IdString("\\OFFSET")).as_int();
@ -775,11 +775,11 @@ struct BtorDumper
else if(cell->type == "$concat")
{
log("writing concat cell\n");
const RTLIL::SigSpec* input_a = &cell->get(RTLIL::IdString("\\A"));
const RTLIL::SigSpec* input_a = &cell->getPort(RTLIL::IdString("\\A"));
int input_a_width = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
log_assert(input_a->size() == input_a_width);
int input_a_line = dump_sigspec(input_a, input_a_width);
const RTLIL::SigSpec* input_b = &cell->get(RTLIL::IdString("\\B"));
const RTLIL::SigSpec* input_b = &cell->getPort(RTLIL::IdString("\\B"));
int input_b_width = cell->parameters.at(RTLIL::IdString("\\B_WIDTH")).as_int();
log_assert(input_b->size() == input_b_width);
int input_b_line = dump_sigspec(input_b, input_b_width);
@ -803,7 +803,7 @@ struct BtorDumper
const RTLIL::SigSpec *output_sig = nullptr;
if (cell->type == "$memrd")
{
output_sig = &cell->get(RTLIL::IdString("\\DATA"));
output_sig = &cell->getPort(RTLIL::IdString("\\DATA"));
}
else if(cell->type == "$memwr" || cell->type == "$assert")
{
@ -811,11 +811,11 @@ struct BtorDumper
}
else if(cell->type == "$dff" || cell->type == "$adff" || cell->type == "$dffsr")
{
output_sig = &cell->get(RTLIL::IdString("\\Q"));
output_sig = &cell->getPort(RTLIL::IdString("\\Q"));
}
else
{
output_sig = &cell->get(RTLIL::IdString("\\Y"));
output_sig = &cell->getPort(RTLIL::IdString("\\Y"));
}
return output_sig;
}

4
backends/spice/spice.cc
View file

@ -79,8 +79,8 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de
for (RTLIL::Wire *wire : ports) {
log_assert(wire != NULL);
RTLIL::SigSpec sig(RTLIL::State::Sz, wire->width);
if (cell->has(wire->name)) {
sig = sigmap(cell->get(wire->name));
if (cell->hasPort(wire->name)) {
sig = sigmap(cell->getPort(wire->name));
sig.extend(wire->width, false);
}
port_sigs.push_back(sig);

80
backends/verilog/verilog_backend.cc
View file

@ -305,17 +305,17 @@ void dump_cell_expr_port(FILE *f, RTLIL::Cell *cell, std::string port, bool gen_
{
if (gen_signed && cell->parameters.count("\\" + port + "_SIGNED") > 0 && cell->parameters["\\" + port + "_SIGNED"].as_bool()) {
fprintf(f, "$signed(");
dump_sigspec(f, cell->get("\\" + port));
dump_sigspec(f, cell->getPort("\\" + port));
fprintf(f, ")");
} else
dump_sigspec(f, cell->get("\\" + port));
dump_sigspec(f, cell->getPort("\\" + port));
}
std::string cellname(RTLIL::Cell *cell)
{
if (!norename && cell->name[0] == '$' && reg_ct.cell_known(cell->type) && cell->has("\\Q"))
if (!norename && cell->name[0] == '$' && reg_ct.cell_known(cell->type) && cell->hasPort("\\Q"))
{
RTLIL::SigSpec sig = cell->get("\\Q");
RTLIL::SigSpec sig = cell->getPort("\\Q");
if (SIZE(sig) != 1 || sig.is_fully_const())
goto no_special_reg_name;
@ -350,7 +350,7 @@ no_special_reg_name:
void dump_cell_expr_uniop(FILE *f, std::string indent, RTLIL::Cell *cell, std::string op)
{
fprintf(f, "%s" "assign ", indent.c_str());
dump_sigspec(f, cell->get("\\Y"));
dump_sigspec(f, cell->getPort("\\Y"));
fprintf(f, " = %s ", op.c_str());
dump_attributes(f, "", cell->attributes, ' ');
dump_cell_expr_port(f, cell, "A", true);
@ -360,7 +360,7 @@ void dump_cell_expr_uniop(FILE *f, std::string indent, RTLIL::Cell *cell, std::s
void dump_cell_expr_binop(FILE *f, std::string indent, RTLIL::Cell *cell, std::string op)
{
fprintf(f, "%s" "assign ", indent.c_str());
dump_sigspec(f, cell->get("\\Y"));
dump_sigspec(f, cell->getPort("\\Y"));
fprintf(f, " = ");
dump_cell_expr_port(f, cell, "A", true);
fprintf(f, " %s ", op.c_str());
@ -373,7 +373,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell)
{
if (cell->type == "$_INV_") {
fprintf(f, "%s" "assign ", indent.c_str());
dump_sigspec(f, cell->get("\\Y"));
dump_sigspec(f, cell->getPort("\\Y"));
fprintf(f, " = ");
fprintf(f, "~");
dump_attributes(f, "", cell->attributes, ' ');
@ -384,7 +384,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell)
if (cell->type == "$_AND_" || cell->type == "$_OR_" || cell->type == "$_XOR_") {
fprintf(f, "%s" "assign ", indent.c_str());
dump_sigspec(f, cell->get("\\Y"));
dump_sigspec(f, cell->getPort("\\Y"));
fprintf(f, " = ");
dump_cell_expr_port(f, cell, "A", false);
fprintf(f, " ");
@ -403,7 +403,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell)
if (cell->type == "$_MUX_") {
fprintf(f, "%s" "assign ", indent.c_str());
dump_sigspec(f, cell->get("\\Y"));
dump_sigspec(f, cell->getPort("\\Y"));
fprintf(f, " = ");
dump_cell_expr_port(f, cell, "S", false);
fprintf(f, " ? ");
@ -418,23 +418,23 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell)
if (cell->type.substr(0, 6) == "$_DFF_")
{
std::string reg_name = cellname(cell);
bool out_is_reg_wire = is_reg_wire(cell->get("\\Q"), reg_name);
bool out_is_reg_wire = is_reg_wire(cell->getPort("\\Q"), reg_name);
if (!out_is_reg_wire)
fprintf(f, "%s" "reg %s;\n", indent.c_str(), reg_name.c_str());
dump_attributes(f, indent, cell->attributes);
fprintf(f, "%s" "always @(%sedge ", indent.c_str(), cell->type[6] == 'P' ? "pos" : "neg");
dump_sigspec(f, cell->get("\\C"));
dump_sigspec(f, cell->getPort("\\C"));
if (cell->type[7] != '_') {
fprintf(f, " or %sedge ", cell->type[7] == 'P' ? "pos" : "neg");
dump_sigspec(f, cell->get("\\R"));
dump_sigspec(f, cell->getPort("\\R"));
}
fprintf(f, ")\n");
if (cell->type[7] != '_') {
fprintf(f, "%s" " if (%s", indent.c_str(), cell->type[7] == 'P' ? "" : "!");
dump_sigspec(f, cell->get("\\R"));
dump_sigspec(f, cell->getPort("\\R"));
fprintf(f, ")\n");
fprintf(f, "%s" " %s <= %c;\n", indent.c_str(), reg_name.c_str(), cell->type[8]);
fprintf(f, "%s" " else\n", indent.c_str());
@ -446,7 +446,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell)
if (!out_is_reg_wire) {
fprintf(f, "%s" "assign ", indent.c_str());
dump_sigspec(f, cell->get("\\Q"));
dump_sigspec(f, cell->getPort("\\Q"));
fprintf(f, " = %s;\n", reg_name.c_str());
}
@ -458,27 +458,27 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell)
char pol_c = cell->type[8], pol_s = cell->type[9], pol_r = cell->type[10];
std::string reg_name = cellname(cell);
bool out_is_reg_wire = is_reg_wire(cell->get("\\Q"), reg_name);
bool out_is_reg_wire = is_reg_wire(cell->getPort("\\Q"), reg_name);
if (!out_is_reg_wire)
fprintf(f, "%s" "reg %s;\n", indent.c_str(), reg_name.c_str());
dump_attributes(f, indent, cell->attributes);
fprintf(f, "%s" "always @(%sedge ", indent.c_str(), pol_c == 'P' ? "pos" : "neg");
dump_sigspec(f, cell->get("\\C"));
dump_sigspec(f, cell->getPort("\\C"));
fprintf(f, " or %sedge ", pol_s == 'P' ? "pos" : "neg");
dump_sigspec(f, cell->get("\\S"));
dump_sigspec(f, cell->getPort("\\S"));
fprintf(f, " or %sedge ", pol_r == 'P' ? "pos" : "neg");
dump_sigspec(f, cell->get("\\R"));
dump_sigspec(f, cell->getPort("\\R"));
fprintf(f, ")\n");
fprintf(f, "%s" " if (%s", indent.c_str(), pol_r == 'P' ? "" : "!");
dump_sigspec(f, cell->get("\\R"));
dump_sigspec(f, cell->getPort("\\R"));
fprintf(f, ")\n");
fprintf(f, "%s" " %s <= 0;\n", indent.c_str(), reg_name.c_str());
fprintf(f, "%s" " else if (%s", indent.c_str(), pol_s == 'P' ? "" : "!");
dump_sigspec(f, cell->get("\\S"));
dump_sigspec(f, cell->getPort("\\S"));
fprintf(f, ")\n");
fprintf(f, "%s" " %s <= 1;\n", indent.c_str(), reg_name.c_str());
@ -489,7 +489,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell)
if (!out_is_reg_wire) {
fprintf(f, "%s" "assign ", indent.c_str());
dump_sigspec(f, cell->get("\\Q"));
dump_sigspec(f, cell->getPort("\\Q"));
fprintf(f, " = %s;\n", reg_name.c_str());
}
@ -547,7 +547,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell)
if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$pmux_safe")
{
int width = cell->parameters["\\WIDTH"].as_int();
int s_width = cell->get("\\S").size();
int s_width = cell->getPort("\\S").size();
std::string func_name = cellname(cell);
fprintf(f, "%s" "function [%d:0] %s;\n", indent.c_str(), width-1, func_name.c_str());
@ -579,13 +579,13 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell)
fprintf(f, "%s" "endfunction\n", indent.c_str());
fprintf(f, "%s" "assign ", indent.c_str());
dump_sigspec(f, cell->get("\\Y"));
dump_sigspec(f, cell->getPort("\\Y"));
fprintf(f, " = %s(", func_name.c_str());
dump_sigspec(f, cell->get("\\A"));
dump_sigspec(f, cell->getPort("\\A"));
fprintf(f, ", ");
dump_sigspec(f, cell->get("\\B"));
dump_sigspec(f, cell->getPort("\\B"));
fprintf(f, ", ");
dump_sigspec(f, cell->get("\\S"));
dump_sigspec(f, cell->getPort("\\S"));
fprintf(f, ");\n");
return true;
}
@ -593,9 +593,9 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell)
if (cell->type == "$slice")
{
fprintf(f, "%s" "assign ", indent.c_str());
dump_sigspec(f, cell->get("\\Y"));
dump_sigspec(f, cell->getPort("\\Y"));
fprintf(f, " = ");
dump_sigspec(f, cell->get("\\A"));
dump_sigspec(f, cell->getPort("\\A"));
fprintf(f, " >> %d;\n", cell->parameters.at("\\OFFSET").as_int());
return true;
}
@ -603,14 +603,14 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell)
if (cell->type == "$bu0")
{
fprintf(f, "%s" "assign ", indent.c_str());
dump_sigspec(f, cell->get("\\Y"));
dump_sigspec(f, cell->getPort("\\Y"));
if (cell->parameters["\\A_SIGNED"].as_bool()) {
fprintf(f, " = $signed(");
dump_sigspec(f, cell->get("\\A"));
dump_sigspec(f, cell->getPort("\\A"));
fprintf(f, ");\n");
} else {
fprintf(f, " = { 1'b0, ");
dump_sigspec(f, cell->get("\\A"));
dump_sigspec(f, cell->getPort("\\A"));
fprintf(f, " };\n");
}
return true;
@ -619,11 +619,11 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell)
if (cell->type == "$concat")
{
fprintf(f, "%s" "assign ", indent.c_str());
dump_sigspec(f, cell->get("\\Y"));
dump_sigspec(f, cell->getPort("\\Y"));
fprintf(f, " = { ");
dump_sigspec(f, cell->get("\\B"));
dump_sigspec(f, cell->getPort("\\B"));
fprintf(f, " , ");
dump_sigspec(f, cell->get("\\A"));
dump_sigspec(f, cell->getPort("\\A"));
fprintf(f, " };\n");
return true;
}
@ -633,17 +633,17 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell)
RTLIL::SigSpec sig_clk, sig_arst, val_arst;
bool pol_clk, pol_arst = false;
sig_clk = cell->get("\\CLK");
sig_clk = cell->getPort("\\CLK");
pol_clk = cell->parameters["\\CLK_POLARITY"].as_bool();
if (cell->type == "$adff") {
sig_arst = cell->get("\\ARST");
sig_arst = cell->getPort("\\ARST");
pol_arst = cell->parameters["\\ARST_POLARITY"].as_bool();
val_arst = RTLIL::SigSpec(cell->parameters["\\ARST_VALUE"]);
}
std::string reg_name = cellname(cell);
bool out_is_reg_wire = is_reg_wire(cell->get("\\Q"), reg_name);
bool out_is_reg_wire = is_reg_wire(cell->getPort("\\Q"), reg_name);
if (!out_is_reg_wire)
fprintf(f, "%s" "reg [%d:0] %s;\n", indent.c_str(), cell->parameters["\\WIDTH"].as_int()-1, reg_name.c_str());
@ -672,7 +672,7 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell)
if (!out_is_reg_wire) {
fprintf(f, "%s" "assign ", indent.c_str());
dump_sigspec(f, cell->get("\\Q"));
dump_sigspec(f, cell->getPort("\\Q"));
fprintf(f, " = %s;\n", reg_name.c_str());
}
@ -920,10 +920,10 @@ void dump_module(FILE *f, std::string indent, RTLIL::Module *module)
for (auto &it : module->cells_)
{
RTLIL::Cell *cell = it.second;
if (!reg_ct.cell_known(cell->type) || !cell->has("\\Q"))
if (!reg_ct.cell_known(cell->type) || !cell->hasPort("\\Q"))
continue;
RTLIL::SigSpec sig = cell->get("\\Q");
RTLIL::SigSpec sig = cell->getPort("\\Q");
if (sig.is_chunk()) {
RTLIL::SigChunk chunk = sig.as_chunk();