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More cleanups related to RTLIL::IdString usage

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This commit is contained in:
Clifford Wolf 2014-08-02 13:11:01 +02:00
parent 14412e6c95
commit b9bd22b8c8
33 changed files with 237 additions and 261 deletions
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2
backends/blif/blif.cc
View file

@ -209,7 +209,7 @@ struct BlifDumper
continue;
}
fprintf(f, ".%s %s", subckt_or_gate(cell->type), cstr(cell->type));
fprintf(f, ".%s %s", subckt_or_gate(cell->type.str()), cstr(cell->type));
for (auto &conn : cell->connections())
for (int i = 0; i < conn.second.size(); i++) {
if (conn.second.size() == 1)

22
backends/btor/btor.cc
View file

@ -428,7 +428,7 @@ struct BtorDumper
{
cell_line = ++line_num;
bool reduced = (cell->type == "$not" || cell->type == "$neg") ? false : true;
str = stringf ("%d %s %d %d", cell_line, cell_type_translation.at(cell->type).c_str(), reduced?output_width:w, l);
str = stringf ("%d %s %d %d", cell_line, cell_type_translation.at(cell->type.str()).c_str(), reduced?output_width:w, l);
fprintf(f, "%s\n", str.c_str());
}
if(output_width < w && (cell->type == "$not" || cell->type == "$neg" || cell->type == "$pos"))
@ -487,13 +487,13 @@ struct BtorDumper
int l2 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\B")), l2_width);
++line_num;
std::string op = cell_type_translation.at(cell->type);
std::string op = cell_type_translation.at(cell->type.str());
if(cell->type == "$lt" || cell->type == "$le" ||
cell->type == "$eq" || cell->type == "$ne" || cell->type == "$eqx" || cell->type == "$nex" ||
cell->type == "$ge" || cell->type == "$gt")
{
if(l1_signed)
op = s_cell_type_translation.at(cell->type);
op = s_cell_type_translation.at(cell->type.str());
}
str = stringf ("%d %s %d %d %d", line_num, op.c_str(), output_width, l1, l2);
@ -521,9 +521,9 @@ struct BtorDumper
int l2 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\B")), l2_width);
++line_num;
std::string op = cell_type_translation.at(cell->type);
std::string op = cell_type_translation.at(cell->type.str());
if(cell->type == "$div" && l1_signed)
op = s_cell_type_translation.at(cell->type);
op = s_cell_type_translation.at(cell->type.str());
else if(cell->type == "$mod")
{
if(l1_signed)
@ -555,7 +555,7 @@ struct BtorDumper
int l1 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\A")), l1_width);
int l2 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\B")), ceil(log(l1_width)/log(2)));
int cell_output = ++line_num;
str = stringf ("%d %s %d %d %d", line_num, cell_type_translation.at(cell->type).c_str(), l1_width, l1, l2);
str = stringf ("%d %s %d %d %d", line_num, cell_type_translation.at(cell->type.str()).c_str(), l1_width, l1, l2);
fprintf(f, "%s\n", str.c_str());
if(l2_width > ceil(log(l1_width)/log(2)))
@ -635,7 +635,7 @@ struct BtorDumper
int s = dump_sigspec(&cell->getPort(RTLIL::IdString("\\S")), 1);
++line_num;
str = stringf ("%d %s %d %d %d %d",
line_num, cell_type_translation.at(cell->type).c_str(), output_width, s, l2, l1);//if s is 0 then l1, if s is 1 then l2 //according to the implementation of mux cell
line_num, cell_type_translation.at(cell->type.str()).c_str(), output_width, s, l2, l1);//if s is 0 then l1, if s is 1 then l2 //according to the implementation of mux cell
fprintf(f, "%s\n", str.c_str());
line_ref[cell->name]=line_num;
}
@ -697,7 +697,7 @@ struct BtorDumper
fprintf(f, "%s\n", str.c_str());
}
++line_num;
str = stringf ("%d %s %d %d %d", line_num, cell_type_translation.at(cell->type).c_str(),
str = stringf ("%d %s %d %d %d", line_num, cell_type_translation.at(cell->type.str()).c_str(),
output_width, reg, next);
fprintf(f, "%s\n", str.c_str());
}
@ -768,7 +768,7 @@ struct BtorDumper
log_assert(output->size() == output_width);
int offset = cell->parameters.at(RTLIL::IdString("\\OFFSET")).as_int();
++line_num;
str = stringf("%d %s %d %d %d %d", line_num, cell_type_translation.at(cell->type).c_str(), output_width, input_line, output_width+offset-1, offset);
str = stringf("%d %s %d %d %d %d", line_num, cell_type_translation.at(cell->type.str()).c_str(), output_width, input_line, output_width+offset-1, offset);
fprintf(f, "%s\n", str.c_str());
line_ref[cell->name]=line_num;
}
@ -784,7 +784,7 @@ struct BtorDumper
log_assert(input_b->size() == input_b_width);
int input_b_line = dump_sigspec(input_b, input_b_width);
++line_num;
str = stringf("%d %s %d %d %d", line_num, cell_type_translation.at(cell->type).c_str(), input_a_width+input_b_width,
str = stringf("%d %s %d %d %d", line_num, cell_type_translation.at(cell->type.str()).c_str(), input_a_width+input_b_width,
input_a_line, input_b_line);
fprintf(f, "%s\n", str.c_str());
line_ref[cell->name]=line_num;
@ -888,7 +888,7 @@ struct BtorDumper
inputs[wire->port_id] = wire;
if (wire->port_output) {
outputs[wire->port_id] = wire;
if (wire->name.find("safety") != std::string::npos )
if (wire->name.str().find("safety") != std::string::npos )
safety.push_back(wire);
}
}

2
backends/edif/edif.cc
View file

@ -108,7 +108,7 @@ struct EdifBackend : public Backend {
log_header("Executing EDIF backend.\n");
std::string top_module_name;
std::map<std::string, std::set<std::string>> lib_cell_ports;
std::map<RTLIL::IdString, std::set<RTLIL::IdString>> lib_cell_ports;
CellTypes ct(design);
EdifNames edif_names;

12
backends/verilog/verilog_backend.cc
View file

@ -39,14 +39,14 @@ namespace {
bool norename, noattr, attr2comment, noexpr;
int auto_name_counter, auto_name_offset, auto_name_digits;
std::map<std::string, int> auto_name_map;
std::map<RTLIL::IdString, int> auto_name_map;
std::set<std::string> reg_wires;
std::set<RTLIL::IdString> reg_wires;
CellTypes reg_ct;
RTLIL::Module *active_module;
void reset_auto_counter_id(const std::string &id, bool may_rename)
void reset_auto_counter_id(RTLIL::IdString id, bool may_rename)
{
const char *str = id.c_str();
@ -94,7 +94,7 @@ void reset_auto_counter(RTLIL::Module *module)
log(" renaming `%s' to `_%0*d_'.\n", it->first.c_str(), auto_name_digits, auto_name_offset + it->second);
}
std::string id(std::string internal_id, bool may_rename = true)
std::string id(RTLIL::IdString internal_id, bool may_rename = true)
{
const char *str = internal_id.c_str();
bool do_escape = false;
@ -324,7 +324,7 @@ std::string cellname(RTLIL::Cell *cell)
if (wire->name[0] != '\\')
goto no_special_reg_name;
std::string cell_name = wire->name;
std::string cell_name = wire->name.str();
size_t pos = cell_name.find('[');
if (pos != std::string::npos)
@ -715,7 +715,7 @@ void dump_cell(FILE *f, std::string indent, RTLIL::Cell *cell)
fprintf(f, " %s (", cell_name.c_str());
bool first_arg = true;
std::set<std::string> numbered_ports;
std::set<RTLIL::IdString> numbered_ports;
for (int i = 1; true; i++) {
char str[16];
snprintf(str, 16, "$%d", i);