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Added RTLIL::Cell::has(portname)

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This commit is contained in:
Clifford Wolf 2014-07-26 16:11:28 +02:00
parent a84cb04935
commit 97a59851a6
12 changed files with 33 additions and 27 deletions
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2
backends/spice/spice.cc
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@ -80,7 +80,7 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de
for (RTLIL::Wire *wire : ports) {
log_assert(wire != NULL);
RTLIL::SigSpec sig(RTLIL::State::Sz, wire->width);
if (cell->connections().count(wire->name) > 0) {
if (cell->has(wire->name)) {
sig = sigmap(cell->connections().at(wire->name));
sig.extend(wire->width, false);
}

4
backends/verilog/verilog_backend.cc
View file

@ -301,7 +301,7 @@ void dump_cell_expr_port(FILE *f, RTLIL::Cell *cell, std::string port, bool gen_
std::string cellname(RTLIL::Cell *cell)
{
if (!norename && cell->name[0] == '$' && reg_ct.cell_known(cell->type) && cell->connections().count("\\Q") > 0)
if (!norename && cell->name[0] == '$' && reg_ct.cell_known(cell->type) && cell->has("\\Q"))
{
RTLIL::SigSpec sig = cell->get("\\Q");
if (SIZE(sig) != 1 || sig.is_fully_const())
@ -908,7 +908,7 @@ void dump_module(FILE *f, std::string indent, RTLIL::Module *module)
for (auto &it : module->cells)
{
RTLIL::Cell *cell = it.second;
if (!reg_ct.cell_known(cell->type) || cell->connections().count("\\Q") == 0)
if (!reg_ct.cell_known(cell->type) || !cell->has("\\Q"))
continue;
RTLIL::SigSpec sig = cell->get("\\Q");