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Refactoring: Renamed RTLIL::Module::cells to cells_

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This commit is contained in:
Clifford Wolf 2014-07-27 01:51:45 +02:00
parent f9946232ad
commit 4c4b602156
61 changed files with 152 additions and 152 deletions
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2
backends/blif/blif.cc
View file

@ -140,7 +140,7 @@ struct BlifDumper
fprintf(f, ".names $true\n1\n");
}
for (auto &cell_it : module->cells)
for (auto &cell_it : module->cells_)
{
RTLIL::Cell *cell = cell_it.second;

6
backends/btor/btor.cc
View file

@ -192,7 +192,7 @@ struct BtorDumper
if(cell_id == curr_cell)
break;
log(" -- found cell %s\n", cstr(cell_id));
RTLIL::Cell* cell = module->cells.at(cell_id);
RTLIL::Cell* cell = module->cells_.at(cell_id);
const RTLIL::SigSpec* cell_output = get_cell_output(cell);
int cell_line = dump_cell(cell);
@ -832,7 +832,7 @@ struct BtorDumper
log("creating intermediate wires map\n");
//creating map of intermediate wires as output of some cell
for (auto it = module->cells.begin(); it != module->cells.end(); ++it)
for (auto it = module->cells_.begin(); it != module->cells_.end(); ++it)
{
RTLIL::Cell *cell = it->second;
const RTLIL::SigSpec* output_sig = get_cell_output(cell);
@ -911,7 +911,7 @@ struct BtorDumper
}
log("writing cells\n");
for(auto cell_it = module->cells.begin(); cell_it != module->cells.end(); ++cell_it)
for(auto cell_it = module->cells_.begin(); cell_it != module->cells_.end(); ++cell_it)
{
dump_cell(cell_it->second);
}

6
backends/edif/edif.cc
View file

@ -143,7 +143,7 @@ struct EdifBackend : public Backend {
if (module->memories.size() != 0)
log_error("Found munmapped emories in module %s: unmapped memories are not supported in EDIF backend!\n", RTLIL::id2cstr(module->name));
for (auto cell_it : module->cells)
for (auto cell_it : module->cells_)
{
RTLIL::Cell *cell = cell_it.second;
if (!design->modules.count(cell->type) || design->modules.at(cell->type)->get_bool_attribute("\\blackbox")) {
@ -215,7 +215,7 @@ struct EdifBackend : public Backend {
std::map<RTLIL::Module*, std::set<RTLIL::Module*>> module_deps;
for (auto &mod_it : design->modules) {
module_deps[mod_it.second] = std::set<RTLIL::Module*>();
for (auto &cell_it : mod_it.second->cells)
for (auto &cell_it : mod_it.second->cells_)
if (design->modules.count(cell_it.second->type) > 0)
module_deps[mod_it.second].insert(design->modules.at(cell_it.second->type));
}
@ -280,7 +280,7 @@ struct EdifBackend : public Backend {
fprintf(f, " (contents\n");
fprintf(f, " (instance GND (viewRef VIEW_NETLIST (cellRef GND (libraryRef LIB))))\n");
fprintf(f, " (instance VCC (viewRef VIEW_NETLIST (cellRef VCC (libraryRef LIB))))\n");
for (auto &cell_it : module->cells) {
for (auto &cell_it : module->cells_) {
RTLIL::Cell *cell = cell_it.second;
fprintf(f, " (instance %s\n", EDIF_DEF(cell->name));
fprintf(f, " (viewRef VIEW_NETLIST (cellRef %s%s))", EDIF_REF(cell->type),

2
backends/ilang/ilang_backend.cc
View file

@ -294,7 +294,7 @@ void ILANG_BACKEND::dump_module(FILE *f, std::string indent, const RTLIL::Module
dump_memory(f, indent + " ", it->second);
}
for (auto it = module->cells.begin(); it != module->cells.end(); it++)
for (auto it = module->cells_.begin(); it != module->cells_.end(); it++)
if (!only_selected || design->selected(module, it->second)) {
if (only_selected)
fprintf(f, "\n");

4
backends/intersynth/intersynth.cc
View file

@ -128,7 +128,7 @@ struct IntersynthBackend : public Backend {
if (module->get_bool_attribute("\\blackbox"))
continue;
if (module->memories.size() == 0 && module->processes.size() == 0 && module->cells.size() == 0)
if (module->memories.size() == 0 && module->processes.size() == 0 && module->cells_.size() == 0)
continue;
if (selected && !design->selected_whole_module(module->name)) {
@ -159,7 +159,7 @@ struct IntersynthBackend : public Backend {
}
// Submodules: "std::set<string> celltypes_code" prevents duplicate cell types
for (auto cell_it : module->cells)
for (auto cell_it : module->cells_)
{
RTLIL::Cell *cell = cell_it.second;
std::string celltype_code, node_code;

2
backends/spice/spice.cc
View file

@ -47,7 +47,7 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de
SigMap sigmap(module);
int cell_counter = 0, conn_counter = 0, nc_counter = 0;
for (auto &cell_it : module->cells)
for (auto &cell_it : module->cells_)
{
RTLIL::Cell *cell = cell_it.second;
fprintf(f, "X%d", cell_counter++);

6
backends/verilog/verilog_backend.cc
View file

@ -79,7 +79,7 @@ void reset_auto_counter(RTLIL::Module *module)
for (auto it = module->wires_.begin(); it != module->wires_.end(); it++)
reset_auto_counter_id(it->second->name, true);
for (auto it = module->cells.begin(); it != module->cells.end(); it++) {
for (auto it = module->cells_.begin(); it != module->cells_.end(); it++) {
reset_auto_counter_id(it->second->name, true);
reset_auto_counter_id(it->second->type, false);
}
@ -905,7 +905,7 @@ void dump_module(FILE *f, std::string indent, RTLIL::Module *module)
if (!noexpr)
{
std::set<std::pair<RTLIL::Wire*,int>> reg_bits;
for (auto &it : module->cells)
for (auto &it : module->cells_)
{
RTLIL::Cell *cell = it.second;
if (!reg_ct.cell_known(cell->type) || !cell->has("\\Q"))
@ -955,7 +955,7 @@ void dump_module(FILE *f, std::string indent, RTLIL::Module *module)
for (auto it = module->memories.begin(); it != module->memories.end(); it++)
dump_memory(f, indent + " ", it->second);
for (auto it = module->cells.begin(); it != module->cells.end(); it++)
for (auto it = module->cells_.begin(); it != module->cells_.end(); it++)
dump_cell(f, indent + " ", it->second);
for (auto it = module->processes.begin(); it != module->processes.end(); it++)