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Using $pos models for $bu0

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This commit is contained in:
Clifford Wolf 2014-09-03 21:20:59 +02:00
parent 5733f4a39d
commit b9cb483f3e
3 changed files with 3 additions and 18 deletions
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17
backends/verilog/verilog_backend.cc
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@ -538,6 +538,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
HANDLE_UNIOP("$not", "~")
HANDLE_UNIOP("$pos", "+")
HANDLE_UNIOP("$bu0", "+")
HANDLE_UNIOP("$neg", "-")
HANDLE_BINOP("$and", "&")
@ -651,22 +652,6 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
return true;
}
if (cell->type == "$bu0")
{
f << stringf("%s" "assign ", indent.c_str());
dump_sigspec(f, cell->getPort("\\Y"));
if (cell->parameters["\\A_SIGNED"].as_bool()) {
f << stringf(" = $signed(");
dump_sigspec(f, cell->getPort("\\A"));
f << stringf(");\n");
} else {
f << stringf(" = { 1'b0, ");
dump_sigspec(f, cell->getPort("\\A"));
f << stringf(" };\n");
}
return true;
}
if (cell->type == "$concat")
{
f << stringf("%s" "assign ", indent.c_str());