Eddie Hung
d9c1664462
Simplify opt_expr tests using equiv_opt
2019-08-09 10:08:17 -07:00
Eddie Hung
8bf45f34c4
Remove dump call
2019-08-07 21:36:02 -07:00
Eddie Hung
2b6cdfb39f
Move tests/various/opt* into tests/opt/
2019-08-07 21:35:48 -07:00
Eddie Hung
d5e8c0e6d3
Remove ice40_unlut call, simply do equiv_opt on synth_ice40
2019-08-07 21:33:56 -07:00
Eddie Hung
35bf509603
Add testcase from removed opt_ff.{v,ys}
2019-08-07 21:31:32 -07:00
Eddie Hung
4545bf482f
Remove tests/opt/opt_ff.{v,ys} as they don't seem to do anything but run
2019-08-07 16:48:38 -07:00
Clifford Wolf
e9a756aa7a
Merge pull request #1213 from YosysHQ/eddie/wreduce_add
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wreduce/opt_expr: improve width reduction for $add and $sub cells
2019-08-07 14:27:35 +02:00
Clifford Wolf
48f7682e32
Merge pull request #1240 from ucb-bar/firrtl-properties+pow+xnor
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Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog semantic differences.
2019-08-07 12:31:32 +02:00
Bogdan Vukobratovic
067b44938c
Fix wrong results when opt_share called before opt_clean
2019-08-07 09:30:58 +02:00
Eddie Hung
2d1b517b01
Add signed opt_expr tests
2019-08-06 15:40:30 -07:00
Eddie Hung
769c750c22
Add signed test
2019-08-06 15:38:43 -07:00
Eddie Hung
51b39219cd
Move LSB tests from wreduce to opt_expr
2019-08-06 15:24:49 -07:00
Eddie Hung
26cb3e7afc
Merge remote-tracking branch 'origin/master' into eddie/wreduce_add
2019-08-06 14:50:00 -07:00
David Shah
3a3da678ad
Add test for writing gzip-compressed files
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Signed-off-by: David Shah <dave@ds0.me>
2019-08-06 17:43:04 +01:00
Bogdan Vukobratovic
6a796accc0
Support various binary operators in opt_share
2019-08-04 19:06:38 +02:00
Bogdan Vukobratovic
d8be5ce6ba
Tabs to spaces in opt_share examples
2019-08-03 12:35:46 +02:00
Bogdan Vukobratovic
280c4e7794
Fix spacing in opt_share tests, change wording in opt_share help
2019-08-03 12:28:46 +02:00
Jim Lawson
3b8c917025
Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog semantic differences.
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Use FIRRTL spec vlaues for definition of FIRRTL widths.
Added support for '$pos`, `$pow` and `$xnor` cells.
Enable tests/simple/operators.v since all operators tested there are now supported.
Disable FIRRTL tests of tests/simple/{defvalue.sv,implicit_ports.v,wandwor.v} since they currently generate FIRRTL compilation errors.
2019-07-31 09:27:38 -07:00
Bogdan Vukobratovic
c075486c59
Reimplement opt_share to work on $alu and $pmux
2019-07-28 16:03:54 +02:00
Bogdan Vukobratovic
07c4a7d438
Implement opt_share
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This pass identifies arithmetic operators that share an operand and whose
results are used in mutually exclusive cases controlled by a multiplexer, and
merges them together by multiplexing the other operands
2019-07-26 11:36:48 +02:00
David Shah
933db0410e
Add support for reading gzip'd input files
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Signed-off-by: David Shah <dave@ds0.me>
2019-07-26 10:23:58 +01:00
Eddie Hung
c926eeb43a
Add another test
2019-07-19 14:02:46 -07:00
Eddie Hung
5bd088a686
Add one more test with trimming Y_WIDTH of $sub
2019-07-19 13:11:30 -07:00
Eddie Hung
415a2716df
Be more explicit
2019-07-19 12:53:18 -07:00
Eddie Hung
4e9b1d36fa
Add tests for sub too
2019-07-19 12:50:11 -07:00
Eddie Hung
3839bd50f2
Add test
2019-07-19 12:43:02 -07:00
Eddie Hung
8a2a2cd035
Forgot to commit
2019-07-16 12:44:26 -07:00
Eddie Hung
dd10d2b00d
Add tests for cmp2lut on LUT6
2019-07-16 12:11:59 -07:00
Eddie Hung
41243a53b3
Update test with more accurate LUT mask
2019-07-12 21:00:59 -07:00
Clifford Wolf
9546ccdbd3
Fix tests/various/async FFL test
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-07-09 22:44:39 +02:00
Clifford Wolf
5138621482
Improve tests/various/async, disable failing ffl test
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-07-09 22:21:25 +02:00
Clifford Wolf
c18b23f055
Add tests/various/async.{sh,v}
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-07-09 20:58:59 +02:00
Clifford Wolf
3dd92fcd15
Improve tests/various/run-test.sh
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-07-09 20:58:28 +02:00
Clifford Wolf
f8512864cd
Add tests/simple_abc9/.gitignore
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-07-09 20:58:01 +02:00
Eddie Hung
de26328130
Merge pull request #1156 from YosysHQ/eddie/fix_abc9_unknown_cell
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write_xaiger to treat unknown cell connections as keep-s
2019-07-03 09:43:00 -07:00
Clifford Wolf
e38b2ac648
Merge pull request #1147 from YosysHQ/clifford/fix1144
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Improve specify dummy parser
2019-07-03 12:30:37 +02:00
Clifford Wolf
1f173210eb
Fix tests/various/specify.v
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-07-03 11:25:05 +02:00
Clifford Wolf
ba36567908
Some cleanups in "ignore specify parser"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-07-03 11:22:10 +02:00
Eddie Hung
9c556e3c02
Add test
2019-07-02 19:13:40 -07:00
Eddie Hung
8455d1f4ff
Merge pull request #1150 from YosysHQ/eddie/script_from_wire
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Add "script -select [selection]" to allow commands to be taken from wires
2019-07-02 10:20:42 -07:00
Eddie Hung
81a717e9b7
Update test for Pass::call_on_module()
2019-07-02 08:22:31 -07:00
Eddie Hung
90382a0f6d
Update test too
2019-07-02 08:19:23 -07:00
David Shah
d45936fe5f
memory_dff: Fix checking of feedback mux input when more than one mux
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Signed-off-by: David Shah <dave@ds0.me>
2019-07-02 13:35:50 +01:00
Eddie Hung
04459cb30a
Comment out invalid syntax
2019-06-30 11:48:01 -07:00
Eddie Hung
fd2fb4f0f0
Merge branch 'master' into eddie/script_from_wire
2019-06-28 14:56:34 -07:00
Eddie Hung
0ec7c09756
autotest.sh to define _AUTOTB when test_autotb
2019-06-28 14:56:22 -07:00
Eddie Hung
64f6b0c747
Try command in another module
2019-06-28 13:41:32 -07:00
Eddie Hung
2c6aaef3db
Add test
2019-06-28 13:32:09 -07:00
Eddie Hung
da5f830395
Merge pull request #1098 from YosysHQ/xaig
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"abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
2019-06-28 10:59:03 -07:00
Eddie Hung
dc677c791d
Add test from #1144 , and try reading without '-specify' flag
2019-06-28 10:12:48 -07:00
