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Remove tests/opt/opt_ff.{v,ys} as they don't seem to do anything but run

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This commit is contained in:
Eddie Hung 2019-08-07 16:48:38 -07:00
parent 9776084eda
commit 4545bf482f
2 changed files with 0 additions and 24 deletions
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21
tests/opt/opt_ff.v
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@ -1,21 +0,0 @@
module top(
input clk,
input rst,
input [2:0] a,
output [1:0] b
);
reg [2:0] b_reg;
initial begin
b_reg <= 3'b0;
end
assign b = b_reg[1:0];
always @(posedge clk or posedge rst) begin
if(rst) begin
b_reg <= 3'b0;
end else begin
b_reg <= a;
end
end
endmodule

3
tests/opt/opt_ff.ys
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@ -1,3 +0,0 @@
read_verilog opt_ff.v
synth_ice40
ice40_unlut