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Implement opt_share

This pass identifies arithmetic operators that share an operand and whose
results are used in mutually exclusive cases controlled by a multiplexer, and
merges them together by multiplexing the other operands
This commit is contained in:
Bogdan Vukobratovic 2019-07-26 11:36:48 +02:00
parent a02d1720a7
commit 07c4a7d438
6 changed files with 383 additions and 1 deletions

15
tests/opt/opt_share_cat.v Normal file
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module add_sub(
input [15:0] a,
input [15:0] b,
input [15:0] c,
input [15:0] d,
input sel,
output [63:0] res,
);
reg [31: 0] cat1 = {a+b, c+d};
reg [31: 0] cat2 = {a-b, c-d};
assign res = {b, sel ? cat1 : cat2, a};
endmodule

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read_verilog opt_share_cat.v
prep -flatten
opt
pmuxtree
opt_share
opt_clean
select -assert-count 2 t:$sub
select -assert-count 0 t:$add

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module add_sub(
input [15:0] a,
input [15:0] b,
input [15:0] c,
input [1:0] sel,
output reg [15:0] res
);
always @* begin
case(sel)
0: res = a + b;
1: res = a - b;
2: res = a + c;
default: res = 16'bx;
endcase
end
endmodule

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read_verilog opt_share_mux_tree.v
prep -flatten
opt
pmuxtree
opt_share;
opt_share;
opt_clean
select -assert-count 1 t:$add
select -assert-count 0 t:$sub