Eddie Hung da5f830395 Merge pull request #1098 from YosysHQ/xaig ... "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)		2019-06-28 10:59:03 -07:00
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aiger	tests: use optional ABCEXTERNAL when specified	2019-06-27 23:00:13 -04:00
arch	Add simcells.v, simlib.v, and some output	2019-06-27 11:13:49 -07:00
asicworld	Fix FIRRTL to Verilog process instance subfield assignment.	2019-02-25 16:18:13 -08:00
bram
errors
fsm
hana
liberty	Liberty file parser now accepts superfluous ;	2019-03-27 15:16:19 +01:00
lut
memories	tests: use optional ABCEXTERNAL when specified	2019-06-27 23:00:13 -04:00
opt	Refactor "opt_rmdff -sat"	2019-06-20 13:44:21 +02:00
realmath
sat	support repeat loops with constant repeat counts outside of constant functions	2019-04-09 12:28:32 -04:00
share
simple	Add test	2019-06-20 16:07:22 -07:00
simple_abc9	Fix issue with part of PI being 1'bx	2019-06-20 17:38:16 -07:00
smv
sva	Fix "verific -extnets" for more complex situations	2019-03-26 14:17:46 +01:00
svinterfaces	Fix typo in tests/svinterfaces/runone.sh	2019-05-03 14:40:51 +02:00
techmap	Move tests/techmap/abc9 to simple_abc9	2019-02-20 15:34:59 -08:00
tools	tests: use optional ABCEXTERNAL when specified	2019-06-27 23:00:13 -04:00
unit
various	Merge remote-tracking branch 'origin/master' into xaig	2019-06-27 11:54:34 -07:00
vloghtb