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Reimplement opt_share to work on $alu and $pmux

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This commit is contained in:
Bogdan Vukobratovic 2019-07-28 16:03:54 +02:00
parent 07c4a7d438
commit c075486c59
21 changed files with 521 additions and 113 deletions
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10
tests/opt/opt_share_add_sub.v Normal file
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@ -0,0 +1,10 @@
module opt_share_test(
input [15:0] a,
input [15:0] b,
input sel,
output [15:0] res,
);
assign res = {sel ? a + b : a - b};
endmodule

13
tests/opt/opt_share_add_sub.ys Normal file
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@ -0,0 +1,13 @@
read_verilog opt_share_add_sub.v
proc;;
copy opt_share_test merged
alumacc merged
opt merged
opt_share merged
opt_clean merged
miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp opt_share_test merged miter
sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter
select -assert-count 1 -module merged t:$alu

2
tests/opt/opt_share_cat.v
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@ -1,4 +1,4 @@
module add_sub(
module opt_share_test(
input [15:0] a,
input [15:0] b,
input [15:0] c,

18
tests/opt/opt_share_cat.ys
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@ -1,9 +1,13 @@
read_verilog opt_share_cat.v
prep -flatten
opt
pmuxtree
opt_share
opt_clean
proc;;
copy opt_share_test merged
select -assert-count 2 t:$sub
select -assert-count 0 t:$add
alumacc merged
opt merged
opt_share merged
opt_clean merged
miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp opt_share_test merged miter
sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter
select -assert-count 2 -module merged t:$alu

22
tests/opt/opt_share_cat_multiuser.v Normal file
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@ -0,0 +1,22 @@
module opt_share_test(
input [15:0] a,
input [15:0] b,
input [15:0] c,
input [15:0] d,
input sel,
output reg [47:0] res,
);
wire [15:0] add_res = a+b;
wire [15:0] sub_res = a-b;
wire [31: 0] cat1 = {add_res, c+d};
wire [31: 0] cat2 = {sub_res, c-d};
always @* begin
case(sel)
0: res = {cat1, add_res};
1: res = {cat2, add_res};
endcase
end
endmodule

13
tests/opt/opt_share_cat_multiuser.ys Normal file
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@ -0,0 +1,13 @@
read_verilog opt_share_cat_multiuser.v
proc;;
copy opt_share_test merged
alumacc merged
opt merged
opt_share merged
opt_clean merged
miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp opt_share_test merged miter
sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter
select -assert-count 3 -module merged t:$alu

21
tests/opt/opt_share_diff_port_widths.v Normal file
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@ -0,0 +1,21 @@
module opt_share_test(
input [15:0] a,
input [15:0] b,
input [15:0] c,
input [1:0] sel,
output reg [15:0] res
);
wire [15:0] add0_res = a+b;
wire [15:0] add1_res = a+c;
always @* begin
case(sel)
0: res = add0_res[10:0];
1: res = add1_res[10:0];
2: res = a - b;
default: res = 32'bx;
endcase
end
endmodule

13
tests/opt/opt_share_diff_port_widths.ys Normal file
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@ -0,0 +1,13 @@
read_verilog opt_share_diff_port_widths.v
proc;;
copy opt_share_test merged
alumacc merged
opt merged
opt_share merged
opt_clean merged
miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp opt_share_test merged miter
sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter
select -assert-count 2 -module merged t:$alu

19
tests/opt/opt_share_extend.v Normal file
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@ -0,0 +1,19 @@
module opt_share_test(
input signed [7:0] a,
input signed [10:0] b,
input signed [15:0] c,
input [1:0] sel,
output reg signed [15:0] res
);
always @* begin
case(sel)
0: res = a + b;
1: res = a - b;
2: res = a + c;
default: res = 16'bx;
endcase
end
endmodule

13
tests/opt/opt_share_extend.ys Normal file
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@ -0,0 +1,13 @@
read_verilog opt_share_extend.v
proc;;
copy opt_share_test merged
alumacc merged
opt merged
opt_share merged
opt_clean merged
miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp opt_share_test merged miter
sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter
select -assert-count 1 -module merged t:$alu

22
tests/opt/opt_share_large_pmux_cat.v Normal file
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@ -0,0 +1,22 @@
module opt_share_test(
input [15:0] a,
input [15:0] b,
input [15:0] c,
input [2:0] sel,
output reg [31:0] res
);
always @* begin
case(sel)
0: res = {a + b, a};
1: res = {a - b, b};
2: res = {a + c, c};
3: res = {a - c, a};
4: res = {b, b};
5: res = {c, c};
default: res = 32'bx;
endcase
end
endmodule

13
tests/opt/opt_share_large_pmux_cat.ys Normal file
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@ -0,0 +1,13 @@
read_verilog opt_share_large_pmux_cat.v
proc;;
copy opt_share_test merged
alumacc merged
opt merged
opt_share merged
opt_clean merged
miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp opt_share_test merged miter
sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter
select -assert-count 1 -module merged t:$alu

25
tests/opt/opt_share_large_pmux_cat_multipart.v Normal file
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@ -0,0 +1,25 @@
module opt_share_test(
input [15:0] a,
input [15:0] b,
input [15:0] c,
input [15:0] d,
input [2:0] sel,
output reg [31:0] res
);
wire [15:0] add0_res = a+d;
always @* begin
case(sel)
0: res = {add0_res, a};
1: res = {a - b, add0_res[7], 15'b0};
2: res = {b-a, b};
3: res = {d, b - c};
4: res = {d, b - a};
5: res = {c, d};
6: res = {a - c, b-d};
default: res = 32'bx;
endcase
end
endmodule

15
tests/opt/opt_share_large_pmux_cat_multipart.ys Normal file
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@ -0,0 +1,15 @@
read_verilog opt_share_large_pmux_cat_multipart.v
proc;;
copy opt_share_test merged
alumacc merged
opt merged
opt_share merged
opt_clean merged
opt -full
miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp opt_share_test merged miter
sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter
select -assert-count 4 -module merged t:$alu

24
tests/opt/opt_share_large_pmux_multipart.v Normal file
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@ -0,0 +1,24 @@
module opt_share_test(
input [15:0] a,
input [15:0] b,
input [15:0] c,
input [15:0] d,
input [2:0] sel,
output reg [15:0] res
);
always @* begin
case(sel)
0: res = a + d;
1: res = a - b;
2: res = b;
3: res = b - c;
4: res = b - a;
5: res = c;
6: res = a - c;
default: res = 16'bx;
endcase
end
endmodule

13
tests/opt/opt_share_large_pmux_multipart.ys Normal file
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@ -0,0 +1,13 @@
read_verilog opt_share_large_pmux_multipart.v
proc;;
copy opt_share_test merged
alumacc merged
opt merged
opt_share merged
opt_clean merged
miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp opt_share_test merged miter
sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter
select -assert-count 2 -module merged t:$alu

22
tests/opt/opt_share_large_pmux_part.v Normal file
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@ -0,0 +1,22 @@
module opt_share_test(
input [15:0] a,
input [15:0] b,
input [15:0] c,
input [2:0] sel,
output reg [15:0] res
);
always @* begin
case(sel)
0: res = a + b;
1: res = a - b;
2: res = a + c;
3: res = a - c;
4: res = b;
5: res = c;
default: res = 16'bx;
endcase
end
endmodule

13
tests/opt/opt_share_large_pmux_part.ys Normal file
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@ -0,0 +1,13 @@
read_verilog opt_share_large_pmux_part.v
proc;;
copy opt_share_test merged
alumacc merged
opt merged
opt_share merged
opt_clean merged
miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp opt_share_test merged miter
sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter
select -assert-count 1 -module merged t:$alu

2
tests/opt/opt_share_mux_tree.v
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@ -1,4 +1,4 @@
module add_sub(
module opt_share_test(
input [15:0] a,
input [15:0] b,
input [15:0] c,

19
tests/opt/opt_share_mux_tree.ys
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@ -1,10 +1,13 @@
read_verilog opt_share_mux_tree.v
prep -flatten
opt
pmuxtree
opt_share;
opt_share;
opt_clean
proc;;
copy opt_share_test merged
select -assert-count 1 t:$add
select -assert-count 0 t:$sub
alumacc merged
opt merged
opt_share merged
opt_clean merged
miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp opt_share_test merged miter
sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter
select -assert-count 1 -module merged t:$alu