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Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog semantic differences.

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Use FIRRTL spec vlaues for definition of FIRRTL widths.
Added support for '$pos`, `$pow` and `$xnor` cells.
Enable tests/simple/operators.v since all operators tested there are now supported.
Disable FIRRTL tests of tests/simple/{defvalue.sv,implicit_ports.v,wandwor.v} since they currently generate FIRRTL compilation errors.
This commit is contained in:
Jim Lawson 2019-07-31 09:27:38 -07:00
parent e8341d949f
commit 3b8c917025
2 changed files with 209 additions and 97 deletions
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4
tests/simple/xfirrtl
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@ -1,10 +1,12 @@
# This file contains the names of verilog files to exclude from verilog to FIRRTL regression tests due to known failures.
arraycells.v inst id[0] of
defvalue.sv Initial value not supported
dff_different_styles.v
dff_init.v Initial value not supported
generate.v combinational loop
hierdefparam.v inst id[0] of
i2c_master_tests.v $adff
implicit_ports.v not fully initialized
macros.v drops modules
mem2reg.v drops modules
mem_arst.v $adff
@ -12,7 +14,6 @@ memory.v $adff
multiplier.v inst id[0] of
muxtree.v drops modules
omsp_dbg_uart.v $adff
operators.v $pow
partsel.v drops modules
process.v drops modules
realexpr.v drops modules
@ -23,5 +24,6 @@ specify.v no code (empty module generates error
subbytes.v $adff
task_func.v drops modules
values.v combinational loop
wandwor.v Invalid connect to an expression that is not a reference or a WritePort.
vloghammer.v combinational loop
wreduce.v original verilog issues ( -x where x isn't declared signed)