Akash Levy
71ba176b50
Merge branch 'YosysHQ:main' into main
2025-11-24 14:04:13 -05:00
Mike Inouye
f098352ae6
Enable xaiger2 pass when not in NDEBUG
2025-11-21 14:23:32 -08:00
Akash Levy
e21324d609
Merge from upstream
2025-11-11 22:52:11 -08:00
KrystalDelusion
529886f7fb
Merge pull request #5473 from YosysHQ/krys/unsized_params
...
Handle unsized params
2025-11-12 07:14:44 +13:00
Emil J. Tywoniak
8f53d21ea7
simplify: refactor specific package import
2025-11-10 14:26:10 +01:00
Rahul Bhagwat
54e5eb1c3c
no use vector
2025-11-08 23:16:52 +05:30
Rahul Bhagwat
224109151d
add specific package imports and tests
2025-11-08 23:05:10 +05:30
Krystine Sherwin
7302bf9a66
Add CONST_FLAG_UNSIZED
...
In order to support unsized constants being used as parameters, the `const` struct needs to know if it is unsized (so that the parameter can be used to set the size).
Add unsized flag to param value serialization and rtlil back-/front-end.
Add cell params to `tests/rtlil/everything.v`.
2025-11-07 17:45:07 +13:00
Krystine Sherwin
a5cc905184
simplify.cc: Fix unsized const in params
2025-11-07 15:52:24 +13:00
Akash Levy
11731c91f4
Merge from upstream
2025-11-04 22:20:34 -08:00
KrystalDelusion
52c108cd6a
Merge pull request #4596 from YosysHQ/emil/path-sep-refactor
...
Refactor getting dirs and filenames from paths to files
2025-11-05 09:12:54 +13:00
Akash Levy
76c12f8f8c
Merge branch 'YosysHQ:main' into main
2025-11-03 13:38:04 -05:00
Mohamed Gaber
dec28f65ae
Merge remote-tracking branch 'donn/pyosys_bugfixes' into merge_pybind11
2025-10-26 02:39:43 +03:00
Robert O'Callahan
25aafab86b
Set port_id for Verific PortBus wires
2025-10-23 20:51:53 +00:00
Emil J
9d21585a4c
Merge pull request #5426 from rocallahan/parse-sigspec
...
Don't stop parsing sigspec after a {} group.
2025-10-15 17:31:11 +02:00
Robert O'Callahan
e099a7d34a
Don't stop parsing sigspec after a {} group.
...
Resolves #5424
2025-10-14 21:18:58 +00:00
Emil J. Tywoniak
5cfe6a9c1e
reduce OS ifdefs, refactor getting dirs and filenames from paths to files
2025-10-14 15:46:17 +02:00
Miodrag Milanovic
1f11b2c529
verific: Add src to message missed in #5406
2025-10-13 15:16:17 +02:00
Miodrag Milanovic
dc959cdf4a
verific: Fix error compiling without VERIFIC_LINEFILE_INCLUDES_COLUMNS
2025-10-13 15:16:17 +02:00
Miodrag Milanovic
9570b39519
verifix: fix bits() deprecation warnings
2025-10-13 09:57:22 +02:00
Miodrag Milanovic
2f8f421dee
verifix: fix bits() deprecation warnings
2025-10-13 09:47:18 +02:00
Akash Levy
54653fc82c
Reenable Verific opt and comment out clock enable muxing
2025-10-12 07:52:32 -07:00
Akash Levy
6993fc2540
Flush during import
2025-10-12 07:52:12 -07:00
Emil J
a80462f27f
Merge pull request #5339 from rocallahan/fast-rtlil-parser
...
Rewrite the RTLIL parser for efficiency
2025-10-08 14:52:37 +02:00
N. Engelhardt
0b6adf832b
verific: print source location of problematic object on import error (if available)
2025-10-03 12:57:49 +02:00
Akash Levy
623c54d513
Only do SFCU if has VHDL
2025-10-02 06:02:39 -07:00
Robert O'Callahan
915ad949f9
Limit the maximum size of parsed RTLIL constants to 1 Gb.
...
Without this check it's trivially easy to crash Yosys with a tiny RTLIL input
by specifying a constant with very large width. Fuzz testers love hitting this
over and over again.
2025-10-01 02:17:22 +00:00
Robert O'Callahan
ac4cb5e460
Implement a handwritten recursive-descent RTLIL parser with minimal copying
2025-10-01 02:17:22 +00:00
Akash Levy
16215b8786
Merge upstream
2025-09-29 20:58:56 -07:00
ShinyKate
30cb72a162
Merge pull request #4125 from povik/read-blif-gate-ff
...
read_blif: Represent sequential elements with gate cells
2025-09-29 08:21:16 -05:00
Akash Levy
507d43a9b8
Fixups
2025-09-28 06:16:07 -07:00
Akash Levy
652a9a63b2
Update to latest and fix all disabled tests
2025-09-28 01:33:08 -07:00
Jannis Harder
4bb4b6c662
verific: Extend -sva-continue-on-err to handle FSM explosion
...
This also rolls back any added cells and wires, since we might have
added a lot of helper logic by the point we detect this.
2025-09-27 21:13:02 +02:00
Jannis Harder
83dd99efb7
verific: New -sva-continue-on-error import option
...
This option allows you to process a design that includes unsupported
SVA. Unsupported SVA gets imported as formal cells using 'x inputs and
with the `unsupported_sva` attribute set. This allows you to get a
complete list of defined properties or to check only a supported subset
of properties. To ensure no properties are unintentionally skipped for
actual verification, even in cases where `-sva-continue-on-error` is
used by default to read and inspect a design, `hierarchy -simcheck` and
`hierarchy -smtcheck` (run by SBY) now ensure that no `unsupported_sva`
property cells remain in the design.
2025-09-24 18:58:54 +02:00
Robert O'Callahan
1e5f920dbd
Remove .c_str() from parameters to log_debug()
2025-09-23 19:10:33 +12:00
Akash Levy
d16ca47549
Merge branch 'YosysHQ:main' into main
2025-09-22 17:47:23 -07:00
Emil J
a78eb9e151
Merge pull request #5315 from YosysHQ/emil/write_rtlil-no-sort
...
write_rtlil: don't sort
2025-09-22 11:14:39 +02:00
Akash Levy
60d969530b
Bump to latest
2025-09-21 01:10:04 -07:00
Jannis Harder
79e05a195d
verilog: Bufnorm cell backend and frontend support
...
This makes the Verilog backend handle the $connect and $input_port
cells. This represents the undirected $connect cell using the `tran`
primitive, so we also extend the frontend to support this.
2025-09-17 14:01:09 +02:00
Robert O'Callahan
a1141f1a4c
Remove some unnecessary .c_str() calls to the result of unescape_id()
2025-09-16 23:12:14 +00:00
Robert O'Callahan
d276529d46
Remove .c_str() calls from parameters to log_file_info()
2025-09-16 23:06:28 +00:00
Robert O'Callahan
548deba259
Remove .c_str() calls from parameters to log_file_warning()
2025-09-16 23:03:45 +00:00
Robert O'Callahan
a7c46f7b4a
Remove .c_str() calls from parameters to log_warning()/log_warning_noprefix()
2025-09-16 23:02:16 +00:00
Robert O'Callahan
d1fd6de6da
Remove .c_str() calls from parameters to log_header()
2025-09-16 23:00:42 +00:00
Robert O'Callahan
5ac6858f26
Remove .c_str() from log_cmd_error() and log_file_error() parameters
2025-09-16 22:59:08 +00:00
Emil J. Tywoniak
73747f6928
read_verilog: add -relativeshare for synthesis reproducibility testing
2025-09-16 15:47:35 +02:00
Robert O'Callahan
1a367b907c
Use fast path for 32-bit Const integer constructor in more places
2025-09-16 03:17:24 +00:00
Robert O'Callahan
f65ca488ec
Update frontends to avoid bits()
2025-09-16 03:17:23 +00:00
Akash Levy
1f9013aad0
Merge branch 'YosysHQ:main' into main
2025-09-15 08:04:00 -07:00
Akash Levy
f5cb0c328f
Bump Yosys to latest
2025-09-13 04:35:52 -07:00
