mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-03 13:07:58 +00:00
Code Activity

Set port_id for Verific PortBus wires

Browse source
This commit is contained in:
Robert O'Callahan 2025-10-23 20:46:11 +00:00
parent 37875fdedf
commit 25aafab86b
2 changed files with 14 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

1
frontends/verific/verific.cc
View file

@ -1576,6 +1576,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
SetIter si ;
Port *port ;
FOREACH_PORT_OF_PORTBUS(portbus, si, port) {
wire->port_id = nl->IndexOf(port) + 1;
import_attributes(wire->attributes, port->GetNet(), nl, portbus->Size());
break;
}

13
tests/verific/port_bus_order.ys Normal file
View file

@ -0,0 +1,13 @@
verific -sv <<EOT
module simple (
input [3:0] I2,
input [3:0] I1,
output [3:0] result
);
assign result = I2 & I1;
endmodule
EOT
verific -import simple
write_verilog verilog_port_bus_order.out
!grep -qF 'simple(I2, I1, result)' verilog_port_bus_order.out