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https://github.com/YosysHQ/yosys
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verific: print source location of problematic object on import error (if available)
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1 changed files with 28 additions and 14 deletions
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@ -166,6 +166,25 @@ string get_full_netlist_name(Netlist *nl)
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return nl->CellBaseName();
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}
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std::string format_src_location(DesignObj *obj)
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{
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if (obj == nullptr || obj->Linefile() == nullptr)
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return std::string();
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#ifdef VERIFIC_LINEFILE_INCLUDES_COLUMNS
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return stringf("%s:%d.%d-%d.%d", LineFile::GetFileName(obj->Linefile()), obj->Linefile()->GetLeftLine(), obj->Linefile()->GetLeftCol(), obj->Linefile()->GetRightLine(), obj->Linefile()->GetRightCol());
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#else
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return stringf("%s:%d", LineFile::GetFileName(obj->Linefile()), LineFile::GetLineNo(obj->Linefile()));
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#endif
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}
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std::string announce_src_location(DesignObj *obj)
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{
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std::string loc = format_src_location(obj);
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if (loc.empty())
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return std::string();
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return loc + ": ";
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}
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#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
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class YosysStreamCallBackHandler : public VerificStreamCallBackHandler
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{
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@ -416,13 +435,8 @@ void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &att
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MapIter mi;
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Att *attr;
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#ifdef VERIFIC_LINEFILE_INCLUDES_COLUMNS
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if (obj->Linefile())
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attributes[ID::src] = stringf("%s:%d.%d-%d.%d", LineFile::GetFileName(obj->Linefile()), obj->Linefile()->GetLeftLine(), obj->Linefile()->GetLeftCol(), obj->Linefile()->GetRightLine(), obj->Linefile()->GetRightCol());
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#else
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if (obj->Linefile())
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attributes[ID::src] = stringf("%s:%d", LineFile::GetFileName(obj->Linefile()), LineFile::GetLineNo(obj->Linefile()));
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#endif
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attributes[ID::src] = format_src_location(obj);
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FOREACH_ATTRIBUTE(obj, mi, attr) {
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if (attr->Key()[0] == ' ' || attr->Value() == nullptr)
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@ -508,7 +522,7 @@ void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &att
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}
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}
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if (p == nullptr)
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log_error("Expected TypeRange value '%s' to be of form \"<binary>\" or <binary>.\n", v);
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log_error("%sExpected TypeRange value '%s' to be of form \"<binary>\" or <binary>.\n", announce_src_location(obj), v);
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}
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#endif
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}
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@ -988,7 +1002,7 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr
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else if (net_cin == net_a_msb)
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cell = module->addSshr(inst_name, IN1, IN2, OUT, true);
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else
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log_error("Can't import Verific OPER_SHIFT_RIGHT instance %s: carry_in is neither 0 nor msb of left input\n", inst->Name());
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log_error("%sCan't import Verific OPER_SHIFT_RIGHT instance %s: carry_in is neither 0 nor msb of left input\n", announce_src_location(inst), inst->Name());
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import_attributes(cell->attributes, inst);
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return true;
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}
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@ -1039,7 +1053,7 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr
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else if (net_cin->IsPwr())
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cell = module->addLe(inst_name, IN1, IN2, net_map_at(inst->GetOutput()), SIGNED);
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else
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log_error("Can't import Verific OPER_LESSTHAN instance %s: carry_in is neither 0 nor 1\n", inst->Name());
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log_error("%sCan't import Verific OPER_LESSTHAN instance %s: carry_in is neither 0 nor 1\n", announce_src_location(inst), inst->Name());
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import_attributes(cell->attributes, inst);
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return true;
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}
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@ -1625,7 +1639,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
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bits_in_word = min<int>(bits_in_word, pr->GetInst()->Input2Size());
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continue;
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}
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log_error("Verific RamNet %s is connected to unsupported instance type %s (%s).\n",
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log_error("%sVerific RamNet %s is connected to unsupported instance type %s (%s).\n", announce_src_location(pr->GetInst()),
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net->Name(), pr->GetInst()->View()->Owner()->Name(), pr->GetInst()->Name());
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}
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@ -1915,7 +1929,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
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{
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RTLIL::Memory *memory = module->memories.at(RTLIL::escape_id(inst->GetInput()->Name()), nullptr);
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if (!memory)
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log_error("Memory net '%s' missing, possibly no driver, use verific -flatten.\n", inst->GetInput()->Name());
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log_error("%sMemory net '%s' missing, possibly no driver, use verific -flatten.\n", announce_src_location(inst), inst->GetInput()->Name());
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int numchunks = int(inst->OutputSize()) / memory->width;
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int chunksbits = ceil_log2(numchunks);
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@ -1946,7 +1960,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
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{
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RTLIL::Memory *memory = module->memories.at(RTLIL::escape_id(inst->GetOutput()->Name()), nullptr);
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if (!memory)
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log_error("Memory net '%s' missing, possibly no driver, use verific -flatten.\n", inst->GetInput()->Name());
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log_error("%sMemory net '%s' missing, possibly no driver, use verific -flatten.\n", announce_src_location(inst), inst->GetInput()->Name());
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int numchunks = int(inst->Input2Size()) / memory->width;
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int chunksbits = ceil_log2(numchunks);
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@ -2167,10 +2181,10 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
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if (inst->IsPrimitive())
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{
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if (!mode_keep)
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log_error("Unsupported Verific primitive %s of type %s\n", inst->Name(), inst->View()->Owner()->Name());
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log_error("%sUnsupported Verific primitive %s of type %s\n", announce_src_location(inst), inst->Name(), inst->View()->Owner()->Name());
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if (!verific_sva_prims.count(inst->Type()))
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log_warning("Unsupported Verific primitive %s of type %s\n", inst->Name(), inst->View()->Owner()->Name());
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log_warning("%sUnsupported Verific primitive %s of type %s\n", announce_src_location(inst), inst->Name(), inst->View()->Owner()->Name());
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}
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import_verific_cells:
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